00 可综合风格的模块实例（附源码）

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---

---

一、组合逻辑电路设计实例

（1）8位带进位端的加法器

//-- modified by xlinxdu, 2022/05/02
module addr_8 
(
  input        cin ,
  input [7:0]  a   ,
  input [7:0]  b   ,

  output       cout,
  output [7:0] sum
);

assign {cout,sum} = a + b + cin;

endmodule

---

（2）指令译码电路

//-- modified by xlinxdu, 2022/05/02
`define plus    3'd0
`define minud   3'd1
`define band    3'd2
`define bor     3'd3
`define unegate 3'd4

module alu
(
  output reg [7:0] out   ,
  input      [2:0] opcode,
  input      [7:0] a     ,
  input      [7:0] b
);

always @ (*) begin
  case (opcode)
    `plus : out = a + b;
    `minus: out = a - b;
    `band : out = a & b;
    `bor  : out = a | b;
    `unegate:out =  ~ a;
    default:out = 8'bx;
  endcase
end
endmodule

---

（3）利用task和电平敏感的always块做冒泡排序

//-- modified by xlinxdu, 2022/05/02
module sort4 
#(
  parameter t = 3
)(
  output reg [t:0] ra,
  output reg [t:0] rb,
  output reg [t:0] rc,
  output reg [t:0] rd

  input      [t:0] a,
  input      [t:0] b,
  input      [t:0] c,
  input      [t:0] d
);  
always @ (*) 
begin:local
  reg [t:0] va,vb,vc,vd;
  {va,vb,vc,vd} = {a,b,c,d};
  sort2(va,vc);
  sort2(vb,vd);
  sort2(va,vb);
  sort2(vb,vc);
  {ra,rb,rc,rd} = {va,vb,vc,vd};
end

task sort2;
  inout [t:0] x,y;
  reg   [t:0] tmp;
  if(x > y)begin
    tmp = x  ;
    x   = y  ;
    y   = tmp;
  end
endtask
endmodule

---

（4）数值比较器

//-- modified by xlinxdu, 2022/05/02
module compare#(
  parameter size = 1
)(
  output           equal,
  input [size-1:0] a,
  input [size-1:0] b  
);
  assign equal = (a == b)?1:0;
endmodule

---

（5）3-8译码器

//-- modified by xlinxdu, 2022/05/02
module decoder
(
  input  [2:0] in,
  output [7:0] out
);
assign out = 1'b1 << in;
endmodule

---

（6）8-3译码器

//-- modified by xlinxdu, 2022/05/02
module encoder(
  input      [7:0] in     ,
  output reg       none_on,
  output reg [2:0] out
);
always @(*)
begin:lical
  integer i;
  out = 0;
  none_on = 1;
  for(i=0;i<8;i=i+1)begin
    if(in[i])begin
      out = i;
      none_on = 0;
    end
  end
end
endmodule

---

（7）多路选择器

//-- modified by xlinxdu, 2022/05/02
module emuxl(
  input  a  ,
  input  b  ,
  input  sel,
  output out
);

assign out = sel?a:b;
  
endmodule

---

（8）奇偶校验位生成器

//-- modified by xlinxdu, 2022/05/02
module parity (
  input  [7:0] input_bus,
  output       even_numbits,
  output       odd_numbits ,
);
assign odd_numbits = ^input_bus;
assign even_numbits = ~odd-numbits;
endmodule

---

（9）三态输出驱动器

//-- modified by xlinxdu, 2022/05/02
module tristl (
  output out,
  input  in,
  input  enable
);
  assign out = enable? in: 'bz;
endmodule

---

（10）三态双向驱动器

//-- modified by xlinxdu, 2022/05/02
module bidir(
  inout  tri_inout,
  output out
  input  in,
  input  en,
  input  b 
);
  assign tri_inout = en?in:'bz;
  assign out = tri_inout ^ b;
endmodule

---

二、时序电路设计实例

（1）触发器

//-- modified by xlinxdu, 2022/05/02
module dff(
  input      clk,
  input      data,
  output reg q
);
always @ (posedge clk) begin
  q <= data;
end
endmodule

---

（2）电平敏感型锁存器1

//-- modified by xlinxdu, 2022/05/02
module latch1(
  input  clk,
  input  data,
  output q
);
assign q = clk?data:q;

endmodule

---

（3）带置位和复位端的电平敏感型锁存器2

//-- modified by xlinxdu, 2022/05/02
module latch2(
  input  clk  ,
  input  set  ,
  input  data ,
  input  reset,
  output q
);
  assign q = reset?0:(set?1:(clk?data:q));
endmodule

---

（4）电平敏感型锁存器3

//-- modified by xlinxdu, 2022/05/02
module latch3(
  input      clk,
  input      data,
  output reg q
);

always @ (clk or data)begin
  if(clk)begin
    q = data;
  end
end
  
endmodule

---

（5）移位寄存器

//-- modified by xlinxdu, 2022/05/02
module shifter(
  input clk,
  input din,
  input clr,
  output reg [7:0] dout
);
always @ (posedge clk)begin
  if(clr)begin
    dout <= 8'b0;
  end
  else begin
    dout <= dout << 1;
    dout[0] <= din
  end
end
endmodule

---

（6）8位计数器

//-- modified by xlinxdu, 2022/05/02
module counter(
  input        clk ,
  input        load,
  input        cin ,
  input  [7:0] data,
  output [7:0] out 
);
always @ (posedge clk)begin
  if(load)begin
    out <= data;
  end
  else begin
    out <= out + cin;
  end
  assign count = &out &cin;
end
  
endmodule

---

作者：xlinxdu
版权：本文是作者原创，版权归作者所有。
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