OS Review Chapter 9: Memory Management

Chapter 9: Memory Management

Background

Program must be brought into memory and placed within a process for it to be run

Base and Limit Registers

A pair of base and limit registers define the logical address space

Multi-step Processing of a User Program

Binding of Instructions and Data to Memory

Address binding of instructions and data to memory addresses can happen at three different stages

Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes.

Load time: Must generate relocatable code if memory location is not known at compile time.

Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps

Logical vs. Physical Address Space

• Logical address–generated by the CPU; also referred to as virtual address.

• Physical address–address seen by the memory unit.

Logical and physical addresses are the same in compile-time and load-time address-binding schemes

logical and physical addresses differ in execution time address-binding scheme

In this case, logical address is also referred to as virtual address. (Logical = Virtual in this course) MMU内存管理单元来决定虚拟地址到物理地址的转换 Memory-Management Unit

The user program deals with logical addresses; it never sees the real physical addresses.

Dynamic Loading

Better memory-space utilization; unused routine is never loaded

Useful when large amounts of code are needed to handle infrequently occurring cases

Dynamic Linking

比动态load更进一步 Both Linking and loading postponed until execution time.

节省内存，灵活性

When a routine is called, its stub is executed. The routine is loaded, the address of that routine replaces the stub, and executes the routine

Operating system needed to check if routine is in another process’ memory address

Dynamic linking is particularly useful for libraries

Swapping

Contiguous Allocation

如何分配给不同的进程使用 如何找到进程要访问的内存地址（寻址）

Monoprogramming systems ：

• 系统
• 用户

Multiprogramming systems：

• Fixed partitions
• variable partitions

Fixed partitions：

Memory is divided into n partitions. Partitioning can be done at the startup time and altered later on. Each partition may have a job queue. Or, all partitions share the same job queue

Variable Partitions ：

Hole–block of available memory–>How to satisfy a request of size n from a list of free holes

• First-fit(首次适配)
• Best-fit(最佳适配)
• Worst-fit(最差适配)

Fragmentation(碎片)

Free memory holes between allocated ones are called external fragmentation外部碎片

memory that is allocated to a partition, but is not used, are called internal fragmentation内部碎片

外部碎片不可避免

Compaction for External Fragmentation

Compaction is possible only if relocation is dynamic, and is done at execution time

compaction scheme can be expensive

AC 连续分配容易通过base和limit寄存器实现内存保护

Paging

不连续分配的一种方法

Divide physical memory into fixed-sized blocks called frames(帧)

Divide logical memory into blocks of same size called pages(页)

• Keep track of all free frames.
• To run a program of size n pages, need to find n free frames and load program.
• Set up a page table to translate logical to physical addresses.
• Internal fragmentation.

平均Internal fragmentation的大小是半个frame/page

Address Translation Scheme

Address generated by CPU is divided into:

• Page number§
• Page offset (d)

logical–> pages

physical–>frames

Implementation of Page Table

• Page table is kept in main memory.
• **Page-table base register (PTBR)**points to the page table

TLB 快表: Hit ratio = α

Effective Access Time (EAT)

​ EAT = (1 + ε) α+ (2 + ε）(1 –α) = 2 + ε- α

Memory Protection

Memory protection implemented by associating protection bit with each frame

Valid-invalid bit:

• valid
• invalid: the page is not in the process’ logical address space

we can use a page table length register (PTLR) that stores the length of a process’s page table.–>a process cannot access the memory beyond its region

Page Table Structure

Hierarchical Page Tables 分级页表：

Break up the logical address space into multiple page tables

Answer： 8 7 9

Hashed Page Tables

Inverted Page Table