Fsm ps2

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //
	
    reg [2:0]state,state_next;
    // State transition logic (combinational)
	always@(*)begin
        if (state[2]==1)
            state_next <= {2'd00,in[3]};
        else
            state_next <= {state[1:0],in[3]};
    end

    // State flip-flops (sequential)
    always@(posedge clk)begin
        if (reset)
            state <= 3'd0;
        else
            state <= state_next;
    end
    // Output logic
    assign done = state[2]==1;
endmodule
// 要注意的就是 第三位是1时，当前的三位done完就失效了,他们的值接下来没有用。新来的in[3] 跑到第一位.