Fsm ps2data

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
	
    reg [2:0]state,state_next;
    reg [23:0]out_bytes_;
    // State transition logic (combinational)
	always@(*)begin
        if (state[2]==1)
            state_next <= {2'd00,in[3]};
        else
            state_next <= {state[1:0],in[3]};
    end
	
    // State flip-flops (sequential)
    always@(posedge clk)begin
        if (reset)
            state <= 3'd0;
        else
            state <= state_next;
    end
    // Output logic
    assign done = state[2]==1;
    always@(posedge clk)begin
        out_bytes_ = {out_bytes_[15:0],in};  
        // 时钟信号来的时候才赋值,done 也是,时钟信号来的时候state才改变，done才改变
        // 所以不能写成 assign out_bytes = {out_bytes[15:0],in};  
    end
    assign out_bytes = out_bytes_;  // 赋个值
endmodule