FPGA
小白也能学好FPGA
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2021-01-09
消抖电路或单脉冲电路 module clockpulse( input Btn_In; input clk,clr_; output reg out; reg delay0,delay1,delay2; ); always @(posedge clk or negedge clr_) begin if(~clr) {delay0,delay1,delay2}<=3’b000; else begin delay0<=Btn_In; delay1<=delay0; delay2<=del原创 2021-01-09 14:30:02 · 78 阅读 · 0 评论 -
HDLBits学习
MUX256to1 module mux_256to1( input [255:0] in, input [7:0] sel, output out ); assign out = in[sel]; endmodule原创 2021-01-07 11:52:21 · 673 阅读 · 0 评论