消抖电路或单脉冲电路
module clockpulse(
input Btn_In;
input clk,clr_;
output reg out;
reg delay0,delay1,delay2;
);
always @(posedge clk or negedge clr_)
begin
if(~clr)
{delay0,delay1,delay2}<=3’b000;
else begin
delay0<=Btn_In;
delay1<=delay0;
delay2<=delay1;
end
end
assign out= delay0&delay1&delay2;
endmodule
如果连续3个时钟周期该信号都为1,则认为开关已经完全断开,输出变为1。