ioCC2530 h头文件内容

最新推荐文章于 2024-09-15 21:38:07 发布

致敬英雄

最新推荐文章于 2024-09-15 21:38:07 发布

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ioCC2530.h是一个针对Texas Instruments CC2530微控制器的头文件，包含了该低功耗SoC的8051内核和2.4 GHz IEEE 802.15.4 RF收发器的定义。文件支持IAR、Keil和SDCC编译器，并提供了SFR（特殊功能寄存器）、SFRBIT（位定义）等宏，用于不同编译器的抽象。同时，它定义了中断向量、SFR（特殊功能寄存器）和一些外设寄存器，如定时器、串口、ADC等。

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/**************************************************************************************************
* - ioCC2530.h -
*
* Header file with definitions for the Texas Instruments CC2530 low-power System-on-Chip:
* an 8051-based MCU with 2.4 GHz IEEE 802.15.4 RF transceiver, and up to 256 kB FLASH.
*
* This file supports IAR, Keil and SDCC compilers.
*
**************************************************************************************************
*/

#ifndef IOCC2530_H
#define IOCC2530_H

/* ------------------------------------------------------------------------------------------------
* Compiler Abstraction
* ------------------------------------------------------------------------------------------------
*/
#ifdef __IAR_SYSTEMS_ICC__
#pragma language=extended
#define SFR(name,addr) __sfr __no_init volatile unsigned char name @ addr;
#define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) \
__sfr __no_init volatile union \
{ \
unsigned char name; \
struct { \
unsigned char bit0 : 1; \
unsigned char bit1 : 1; \
unsigned char bit2 : 1; \
unsigned char bit3 : 1; \
unsigned char bit4 : 1; \
unsigned char bit5 : 1; \
unsigned char bit6 : 1; \
unsigned char bit7 : 1; \
}; \
} @ addr;
#define SBIT(name,addr) /* not in use for IAR C Compiler */
#define XREG(addr) ((unsigned char volatile __xdata *) 0)[addr]
#define PXREG(addr) ((unsigned char volatile __xdata *) addr)
#define VECT(num,addr) addr

#elif defined __IAR_SYSTEMS_ASM__
#define SFR(name,addr) name DEFINE addr
SFRBITMACRO MACRO t, addr, bit7 , bit6, bit5, bit4, bit3, bit2, bit1, bit0
t DEFINE addr
bit7 DEFINE addr.7
bit6 DEFINE addr.6
bit5 DEFINE addr.5
bit4 DEFINE addr.4 ;; NB: do not modify indentation of this macro
bit3 DEFINE addr.3
bit2 DEFINE addr.2
bit1 DEFINE addr.1
bit0 DEFINE addr.0
ENDM
#define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) \
SFRBITMACRO <name>, <addr>, <bit7>, <bit6>, <bit5>, <bit4>, <bit3>, <bit2>, <bit1>, <bit0>
#define SBIT(name,addr) name DEFINE addr
#define XREG(addr) addr
#define VECT(num,addr) addr
/* IAR assembler uses some predefined registers. The following prevents name collisions. */
#define SP SPx
#define ACC ACCx
#define B Bx
#define PSW PSWx
#define CY CYx
#define AC ACx
#define F0 F0x
#define RS1 RS1x
#define RS0 RS0x
#define OV OVx
#define P Px

#elif defined __KEIL__
#define SFR(name,addr) sfr name = addr;
#define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) \
sfr name = addr; \
sbit bit7 = addr^7; \
sbit bit6 = addr^6; \
sbit bit5 = addr^5; \
sbit bit4 = addr^4; \
sbit bit3 = addr^3; \
sbit bit2 = addr^2; \
sbit bit1 = addr^1; \
sbit bit0 = addr^0;
#define SBIT(name,addr) sbit name = addr;
#define VECT(num,addr) num

#ifdef __C51__
#define XREG(addr) ((unsigned char volatile xdata *) 0)[addr]
#define PXREG(addr) ((unsigned char volatile __xdata *) addr)
#elif defined __AX51__ || defined __A51__
#define XREG(addr) addr
#define PXREG(addr) addr
#else
#error "Unknown Keil compiler."
#endif

#elif defined SDCC
#define SFR(name, addr) __sfr __at(addr) name;
#define SBIT(name, addr, bit) __sbit __at(addr+bit) name;
#define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) \
__sfr __at(addr) name; \
__sbit __at(addr+7) bit7; \
__sbit __at(addr+6) bit6; \
__sbit __at(addr+5) bit5; \
__sbit __at(addr+4) bit4; \
__sbit __at(addr+3) bit3; \
__sbit __at(addr+2) bit2; \
__sbit __at(addr+1) bit1; \
__sbit __at(addr+0) bit0;
#define XREG(addr) ((__xdata volatile unsigned char *) 0)[addr]
#define PXREG(addr) ((__xdata volatile unsigned char *) addr)
#define VECT(num,addr) num

#else
#error "Unrecognized compiler."
#endif

/* ------------------------------------------------------------------------------------------------
* Interrupt Vectors
* ------------------------------------------------------------------------------------------------
*/
#define RFERR_VECTOR VECT( 0, 0x03 ) /* RF TX FIFO Underflow and RX FIFO Overflow */
#define ADC_VECTOR VECT( 1, 0x0B ) /* ADC End of Conversion */
#define URX0_VECTOR VECT( 2, 0x13 ) /* USART0 RX Complete */
#define URX1_VECTOR VECT( 3, 0x1B ) /* USART1 RX Complete */
#define ENC_VECTOR VECT( 4, 0x23 ) /* AES Encryption/Decryption Complete */
#define ST_VECTOR VECT( 5, 0x2B ) /* Sleep Timer Compare */
#define P2INT_VECTOR VECT( 6, 0x33 ) /* Port 2 Inputs */
#define UTX0_VECTOR VECT( 7, 0x3B ) /* USART0 TX Complete */
#define DMA_VECTOR VECT( 8, 0x43 ) /* DMA Transfer Complete */
#define T1_VECTOR VECT( 9, 0x4B ) /* Timer 1 (16-bit) Capture/Compare/Overflow */
#define T2_VECTOR VECT( 10, 0x53 ) /* Timer 2 (MAC Timer) */
#define T3_VECTOR VECT( 11, 0x5B ) /* Timer 3 (8-bit) Capture/Compare/Overflow */
#define T4_VECTOR VECT( 12, 0x63 ) /* Timer 4 (8-bit) Capture/Compare/Overflow */
#define P0INT_VECTOR VECT( 13, 0x6B ) /* Port 0 Inputs */
#define UTX1_VECTOR VECT( 14, 0x73 ) /* USART1 TX Complete */
#define P1INT_VECTOR VECT( 15, 0x7B ) /* Port 1 Inputs */
#define RF_VECTOR VECT( 16, 0x83 ) /* RF General Interrupts */
#define WDT_VECTOR VECT( 17, 0x8B ) /* Watchdog Overflow in Timer Mode */

/* ------------------------------------------------------------------------------------------------
* SFRs
* ------------------------------------------------------------------------------------------------
*/

/*
* SFRs with an address ending with 0 or 8 are bit accessible.
* They are defined with the SFRBIT() macro that sets the name of each bit.
*/

/* Port 0 */
SFRBIT( P0 , 0x80, P0_7, P0_6, P0_5, P0_4, P0_3, P0_2, P0_1, P0_0 )
SFR( SP , 0x81 ) /* Stack Pointer */
SFR( DPL0 , 0x82 ) /* Data Pointer 0 Low Byte */
SFR( DPH0 , 0x83 ) /* Data Pointer 0 High Byte */
SFR( DPL1 , 0x84 ) /* Data Pointer 1 Low Byte */
SFR( DPH1 , 0x85 ) /* Data Pointer 1 High Byte */
SFR( U0CSR , 0x86 ) /* USART 0 Control and Status */
SFR( PCON , 0x87 ) /* Power Mode Control */

/* Interrupt Flags */
SFRBIT( TCON , 0x88, URX1IF, _TCON6, ADCIF, _TCON4, URX0IF, IT1, RFERRIF, IT0 )
SFR( P0IFG , 0x89 ) /* Port 0 Interrupt Status Flag */
SFR( P1IFG , 0x8A ) /* Port 1 Interrupt Status Flag */
SFR( P2IFG , 0x8B ) /* Port 2 Interrupt Status Flag */
SFR( PICTL

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