Verilog 三角波

//三角波发生器
`timescale 1ns/10ps
module tri_gen(
	clk,
	res,
	d_out);
input clk,res;
output d_out;

reg  state;
reg[8:0] d_out;
always@(posedge clk or negedge res)
       if(~res) begin
       			state<=0;
       			d_out<=0;

              end
      else  begin
      	case(state)
      	0:d_out<=d_out+1;
      	1:d_out<=d_out-1;
      	endcase
          if(d_out==299) state<=1;
          if(d_out==1) state<=0;


          end
endmodule
module tri_gen_tb;
reg clk,res;
wire[8:0] d_out;

tri_gen tri_gen(
	.clk(clk),
	.res(res),
	.d_out(d_out)
	);

initial begin
        clk<=0;res<=0;

     #17 res<=1;
     #8000 $stop;  

end
always #5 clk=~clk;
endmodule

结果：