设计一个序列检测器，检测序列为“11101000”Design a sequence detector with the detection sequence of “11101000“

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分类专栏： Verilog练习文章标签： verilog

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该博客介绍了一个使用Verilog编写的序列检测器，其目标是检测输入数据流中是否存在特定序列"11101000"。模块包含输入时钟、复位信号、数据输入和检测标志输出。通过状态机实现，当检测到匹配序列时，check_flag置位。

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设计一个序列检测器，检测序列为“11101000”

Design a sequence detector with the detection sequence of "11101000"

module sequ_detect(				//检测序列11101000
	input clk,
	input reset_n,
	input data_in,
	output check_flag
);
	localparam s0 = 0, s1= 1, s2 = 2, s3 = 3,
				 s4 = 4, s5 = 5, s6 = 6, s7 = 7, s8 = 8;
	reg [3:0] c_st,next_st;
	always @(posedge clk,negedge reset_n)
		if(!reset_n)
			c_st <= 0;
		else
			c_st <= next_st;
	always @*
			case(c_st)
				s0	:	if(data_in==1) next_st = s1;	else next_st = s0;		
				s1	:	if(data_in==1) next_st = s2;	else next_st = s0;		
				s2	:	if(data_in==1) next_st = s3;	else next_st = s0;		
				s3	:	if(data_in==0) next_st = s4;	else next_st = s3;	
				s4	:	if(data_in==1) next_st = s5;	else next_st = s0;	
				s5	:	if(data_in==0) next_st = s6;	else next_st = s2;	
				s6	:	if(data_in==0) next_st = s7;	else next_st = s1;		
				s7	:	if(data_in==0) next_st = s8;	else next_st = s1;	
				s8	:	if(data_in==0) next_st = s0;	else next_st = s1;	
				default : next_st = s0;
			endcase
	assign check_flag = (c_st == s8) ;
endmodule