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设计一个16-4优先编码器Design a 16-4 priority encoder.
module dec16_4x( input [15:0] x, output reg[3:0] y);reg [15:0] i;always @*begin y = 0; i = 0; repeat(16) begin if(~x[i]) y=i; i=i+1; endendendmodule原创 2021-07-07 11:48:47 · 1313 阅读 · 0 评论 -
设计一个4-16译码器Design a 4-16 decoder.
module dec4_16x( input [3:0] x, output [15:0] y, // High level output output [15:0] yn // Low level output);assign y = 1 << x;assign yn = ~y;endmodule原创 2021-07-07 11:48:06 · 774 阅读 · 0 评论 -
已知输入时钟为20MHz,在Quartus中调用PLL,输出100MHz、75MHz两个时钟,请例化该pll模块。
已知输入时钟为20MHz,在Quartus中调用PLL,输出100MHz、75MHz两个时钟,请例化该pll模块。With a 20MHz input clock, use PLL in Quartus to generate two output clocks, 100MHz and 75MHz. Please instantiate the PLL module.module xpll_inst( input clk_20M, input reset, output clk_100M,原创 2021-07-07 11:47:16 · 618 阅读 · 0 评论 -
设计60进制计数器,带异步复位、同步使能、同步装载、同步清零、同步置位
设计60进制计数器,带异步复位、同步使能、同步装载、同步清零、同步置位Design a modulus 60 counter, with asynchronous reset, synchronous enable, synchronous load, synchronous clear, synchronous set.module cnt60x( input clk, input reset, input [5:0] d, input en, input load, input原创 2021-07-05 23:52:59 · 2728 阅读 · 0 评论 -
设计一个32位ALU支持加法、减法、与、或、异或、取非这六中运算
设计一个32位ALU支持加法、减法、与、或、异或、取非这六中运算Design a 32-bit ALU to support six operations including addition, subtraction, and, or, xor, not.module ALU_32( input [31:0] data_a_in, input [31:0] data_b_in, input carry_in, input [3:0] op_code, output reg carry_原创 2021-07-05 23:51:21 · 1181 阅读 · 0 评论 -
设计一个16位串入并出移位寄存器Design a 16-bit serial-in-parallel-out shift register
module shifter_s1p16( //串行右移专并行输出 input clk, input reset_n, input serial_in, output reg [15:0] parallel_out); always@(posedge clk or negedge reset_n) if(!reset_n) parallel_out <= 0; else parallel_out <= {serial_in, parallel_out[15:.原创 2021-07-05 23:50:30 · 753 阅读 · 0 评论 -
设计一个脉冲发生器,已知系统时钟为50MHz,生成脉冲宽度为1ms,脉冲间隔可调,最大间隔为1s
设计一个脉冲发生器,已知系统时钟为50MHz,生成脉冲宽度为1ms,脉冲间隔可调,最大间隔为1sDesign a pulse generator. The system clock is known to be 50MHz, the pulse width is 1ms, the pulse interval is adjustable, and the maximum interval is 1s.module pulse_gen #( parameter N = 26,parameter原创 2021-07-05 23:49:23 · 1167 阅读 · 0 评论 -
设计一个16选1选择器Design a 16-to-1 selector
设计一个16选1选择器Design a 16-to-1 selectormodule mux16_1( input [3:0] sel, input [15:0] D, output Y);assign Y = D[sel];endmodule原创 2021-07-05 23:48:18 · 658 阅读 · 1 评论 -
设计一个序列检测器,检测序列为“11101000”Design a sequence detector with the detection sequence of “11101000“
设计一个序列检测器,检测序列为“11101000”Design a sequence detector with the detection sequence of "11101000"module sequ_detect( //检测序列11101000 input clk, input reset_n, input data_in, output check_flag); localparam s0 = 0, s1= 1, s2 = 2, s3 = 3, s4 = 4原创 2021-07-05 23:47:09 · 725 阅读 · 0 评论 -
设计一个可以预置分频器,最大分频系数为100000
设计一个可以预置分频器,最大分频系数为100000 Design a preset frequency divider with a maximum frequency dividing coefficient of 100000.module freq_div#( parameter N = 17 )( input clk, input reset_n, input [N-1:0] period_param, input [N-1:0] duty_param, out..原创 2021-07-05 23:43:19 · 551 阅读 · 0 评论 -
设计n位乘加器(先乘后加)Design a n-bit multiplier (firstly multiply and then add)
module MAC_N#( parameter N = 16)( input [N - 1: 0 ] A, input [N - 1: 0 ] B, input [N - 1: 0 ] C, output [2*N - 1 : 0] R); assign R = A * B + C;endmodule原创 2021-07-05 23:41:17 · 135 阅读 · 0 评论 -
设计4位BCD十进制计数器Design a 4-digit BCD decimal counter
module bcd_4d_cnt( //4位十进制计数器 input clk, input reset_n, input en, input load, input [15:0] d, output reg [15:0] bcd); always @ (posedge clk or negedge reset_n) if(!reset_n) bcd <= 0; else i...原创 2021-07-05 23:37:40 · 1468 阅读 · 0 评论