设计一个脉冲发生器，已知系统时钟为50MHz，生成脉冲宽度为1ms，脉冲间隔可调，最大间隔为1s

设计一个脉冲发生器，已知系统时钟为50MHz，生成脉冲宽度为1ms，脉冲间隔可调，最大间隔为1s

Design a pulse generator. The system clock is known to be 50MHz, the pulse width is 1ms, the pulse interval is adjustable, and the maximum interval is 1s.

module pulse_gen	
#(
	parameter N = 26,
parameter DUTY = 1000*50,
parameter PERIOD_MAX = 50*1000*1000	
)
(			//分频器，周期为div_param
	input clk,
	input reset_n,
	input [N-1:0] period_param,
	output reg div_out
);
	reg [N-1:0] cnt;
	always @(posedge clk or negedge reset_n)
		if(!reset_n)
			cnt <= 0;
		else if(cnt < period_param-1 && cnt < PERIOD_MAX-1)
			cnt <= cnt + 1'b1;
		else
			cnt <= 0;	
	always @(posedge clk or negedge reset_n)
		if(!reset_n)
			div_out <= 0;
		else if(cnt < DUTY-1)
			div_out <= 1'b1;
		else 
			div_out <= 0;
endmodule