VHDL产生序列信号发生器

VHDL产生序列信号发生器，，采用两个不同的时钟，产生“01111110”的序列，序列检测机请看下一篇文章

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity senqgen is
port( clk,clr,clock:in std_logic;--两个不同的时钟，一个清零
		zo:out std_logic
		);
end entity;

architecture one of senqgen is

signal	count:std_logic_vector(2 downto 0);--3位宽度产生八位计数状态
signal	z:std_logic:='0';--产生的序列值

begin
	process(clk,clr)
	begin
		if clr='1' then--异步清零
			count<="000";
		else
			if clk'event and clk='1' then
				if count="111" then
					count<="000";
				else
					count<=count+'1';--计数
				end if;
			end if;
		end if;
	end process;
	
	process(count)
	begin
		case count is
			when "000" => z<='0';
			when "001" => z<='1';
			when "010" => z<='1';
			when "011" => z<='1';
			when "100" => z<='1';
			when "101" => z<='1';
			when "110" => z<='1';
			when others => z<='0';--count="111"放在了when others中
		end case;
	end process;
	
	process(clock,z)
	begin
		if clock'event and clock='1' then--使用了另外一个时钟信号
			zo<=z;
		end if;
	end process;

end architecture;