VHDL实现序列检测机

VHDL实现序列检测机，所检测的序列为"01111110"，序列发生器请看上一篇文章

library ieee;
use ieee.std_logic_1164.all;

entity detect is
port( datain:in std_logic;
		clk:in std_logic;
		q:out std_logic
		);
end entity;

architecture one of detect is

type statetype is(s0,s1,s2,s3,s4,s5,s6,s7,s8);

begin
	process
		variable present_state:statetype;
	begin
		q<='0';
		case present_state is
			when s0 =>
				if datain='0' then present_state:=s1;
				else present_state:=s0;end if;
			when s1 =>
				if datain='1' then present_state:=s2;
				else present_state:=s1;end if;
			when s2 =>
				if datain='1' then present_state:=s3;
				else present_state:=s1;end if;
				--由于我们检测的序列是“01111110”,所以当中途出现0的时候，就需要重新检测
				--因此跳转到s1重新开始，s0本来检测的就是0，所以不需要从0开始
			when s3 =>
				if datain='1' then present_state:=s4;
				else present_state:=s1;end if;
			when s4 =>
				if datain='1' then present_state:=s5;
				else present_state:=s1;end if;
			when s5 =>
				if datain='1' then present_state:=s6;
				else present_state:=s1;end if;
			when s6 =>
				if datain='1' then present_state:=s7;
				else present_state:=s1;end if;
			when s7 =>
				if datain='0' then present_state:=s8;q<='1';
				else present_state:=s0;end if;
			when s8 =>
				if datain='0' then present_state:=s1;
				else present_state:=s2;end if;
		end case;
		wait until clk='1';--时钟上升沿
	end process;
	
end architecture;

但是，上面的序列检测机较为繁琐，下面展示一种更为简洁的序列检测机

library ieee;
use ieee.std_logic_1164.all;

entity detect_s is
port( clk,datain:in std_logic;
		q:out std_logic
		);
end entity;

architecture one of detect_s is

signal	reg:std_logic_vector(7 downto 0);

begin
	process(clk)
	begin
		if clk'event and clk='1' then
			reg(0)<=datain;
			reg(7 downto 1)<=reg(6 downto 0);
		end if;
		if reg="01111110" then
			q<='1';
		else
			q<='0';
		end if;
	end process;
	
end architecture;