2021-06-04

一、实验名称：
1.Verilog HDL测试模块；
2.时序逻辑的测试模块。
二、实验目的：
1.实行简单的仿真。
三、实验截图
实验一：
实验代码
module decoder3x8 (din, en,dout,ex);
input [2:0] din;
input en;
output [7:0] dout;
output ex;
reg [7:0] dout;
reg ex;
always @(din or en)
if (en)
begin
dout=8’b1111_1111;
ex=1’b1;
end
else
begin
case (din)
3’b000:begin
dout=8’b1111_1110;
ex=1’b0;
end
3’b001: begin
dout=8’b1111_1101;
ex=1 'b0;
end
3’b010: begin
dout=8’b1111_1011;
ex=1’b0;
end
3’b011: begin
dout=8’b1111_0111;
ex=1’b0;
end
3’b100: begin
dout=8’b1110_1111 ;
ex=1’b0;
end
3’b101: begin
dout=8’b1101_1111;ex=1 'b0;
end
3’b110: begin
dout=8’b1011_1111 ;ex=1’b0;
end
3’b111: begin
dout=8’b0111_1111;
ex=1 'b0;
end
default: begin
dout=8 'b1111_1111 ;
ex=1’b0;
end
endcase
end
endmodule
实验二：

实验代码

module p2s (data_in,clock, reset, load, data_out, done);
input [3:0] data_in;
input clock, reset,load;
output data_out;
output done;
reg done;
reg [3:0] temp;
reg [3:0] cnt;
always@(posedge clock or posedge reset)
if (reset)
begin
temp<=0;
cnt<=0;
done<=1;
end
else if (load)
begin
temp<=data_in;
cnt<=0;
done<=0;
end
else if (cnt3)
begin
temp <= {temp[2:0],1’b0};
cnt<=0;
done<=1;
end
else
begin
temp<={temp[2:0],1’b0};
cnt<=cnt+1;
done<=0;
end
assign data_out=(done1)?1’bz:temp[3];
endmodule

module tbp2s;
reg [3:0] data_in;
reg clock, reset, load;
wire data_out;
wire done;
initial
begin
reset=1;
#15 reset=0;
end
initial clock=1;
always #5 clock=~clock;
always @ (done)
begin
if (done1)
begin
data_in=$random%16;
load=1;
end
else
begin
load=0;
end
end
always @ (posedge clock)
if (load1)
begin:dis
integer i;
i=3;
repeat (4)
begin
@ (posedge clock)
if (data_out==data_in[i])
$display (“Output Right!”);
else
$display (“Bad Output!data_out=%b ,but data_in[%d]=%b”,data_in[i]);
i=i-1;
end
end
p2s ip2s (data_in, clock, reset, load,data_out, done);
endmodule