2021-06-11

独热码状态机

1.设计所需要的功能模块
2.验证所设计模块的正确性
3.代码:
module ex8_1(clock,reset,x,y1,y2);
input clock,reset;input x;output y1,y2;reg y1,y2;reg[3:0] cstate,nstate;parameter s0=4’b0001,s1=4’b0010, s2=4’b0100,s3=4’b1000; always @(posedge clock or posedge reset) begin if(reset) cstate<=s0; else cstate<=nstate;endalways @(cstate or x) begin case(cstate) s0:begin if(x0) nstate=s1; else nstate=s3; end s1:begin if(x0) nstate=s2; else nstate=s0; end s2:begin if(x0) nstate=s3; else nstate=s1; end s3:begin if(x0) nstate=s0; else nstate=s2; end default:nstate=s0; endcaseendalways @(cstate or x) begin case(cstate) s0:begin if(x0) y1=1; else y1=0; end s1:begin if(x0) y1=0; else y1=0; end s2:begin if(x0) y1=0; else y1=0; end s3:begin if(x0) y1=0; else y1=1; end default:y1=0; endcaseendalways @(cstate or x) begin if(cstates0 && x0) y2=1; else if(cstates3 && x1) y2=1; else y2=0;endendmodulemodule tb_ex81;reg x,clock,reset;wire y1,y2;initial clock=0;always #5 clock=~clock;initialbegin reset=0; #15 reset=1; #15 reset=0; #10000 $stop;endinitialbegin #10 x=1; #500 x=0;endex8_1 myex81(clock,reset,x,y1,y2);endmodule