1.设计所需要的功能模块
2.验证所设计模块的正确性
3.代码: module my_rs(reset,set,q,qbar);
input reset,set;
output q,qbar;
nor #(1) n1(q,reset,qbar);
nor #(1) n2(qbar,set,q);
endmodule module tb_71;
reg set,reset;
wire q,qbar;
initialbegin set<=0;
reset<=1;#10 set<=0;
reset<=0;#10 set<=1;
reset<=0;
10 set<=1;
reset<=1;
endmy_rs rs1(reset,set,q,qbar);
initial monitor ( monitor( monitor(time,“set= %b,reset= %b,q= %b,qbar= %b”,set,reset,q,qbar);
endmodule
截图: