1、模块准备
首先,我们先写好一个模块,如our_OnOff.v:
module our_OnOff(
input a,
input b,
output f
);
assign f = a ^ b;
endmodule
2、测试模块
main.c 如下:
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include "Vour_OnOff.h" //因为创建的是our_OnOff.v 所以头文件要包含Vour_OnOff.h(把V放在前面)
int main(int argc,char **argv)
{
Verilated::commandArgs(argc,argv);
Vour_OnOff *top = new Vour_OnOff("top");
while(!Verilated::gotFinish())
{
int a = rand() & 1;
int b = rand() & 1;
top->a = a;
top->b = b;
top->eval();
printf("a = %d, b = %d, f = %d\n",a,b, top->f);
assert(top->f == a ^ b);
}
delete top;
return 0;
}
在一次循环中, 代码将会随机生成两个1比特信号, 用来驱动两个输入端口, 然后通过eval()
函数更新电路的状态, 这样我们就可以读取输出端口的值并打印. 为了自动检查结果是否正确, 我们通过assert()
语句对输出结果进行检查.
3、运行仿真
运行仿真分成三步:
a、生成目标文件夹
verilator -Wall --cc --exe --build main.cpp our_OnOff.v
-
-Wall so Verilator has stronger lint warnings enabled.
-
--cc to get C++ output (versus e.g. SystemC or only linting).
-
--exe, along with our sim_main.cpp wrapper file, so the build will create an executable instead of only a library.
-
--build so Verilator will call make itself. This is we don’t need to manually call make as a separate step. You can also write your own compile rules, and run make yourself as we show in Example SystemC Execution.)
-
An finally, our_OnOff.v which is our SystemVerilog design file.
运行完后会在当前目录生成obj_dir文件夹,这么多文件不需要深究。
b、编译
make -C obj_dir -f Vour_OnOff.mk Vour_OnOff
- Vour_OnOff.mk 也是生成出来的一个文件,在 obj_dir 文件夹里面,用于自动化的编译控制
- 最后一个参数是输出可执行文件的文件名,最好不要乱改,就"V" + "design_name"
c、运行
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