【MIPS五级流水线】Verilog

【这篇博客单纯只是想用来记录一下自己做的实验，详细的代码实在是太多了也没写啥注释，就放一小部分吧】

MIPS五级流水线基本是在单周期处理器的基础上增加4个流水线寄存器以及冲突单元实现的
能实现基础功能的电路图在黑书系列《数字设计和计算机体系结构》里面可以翻到，对着把一个个模块写出来就好啦

但是如果要实现一些别的指令，可能需要更改数据通路和冲突单元，有的甚至还需要更改控制单元的控制信号

PC

module PC (
    input clk,
    input rst,
    input en,
    input pcwrite,
    input [31:0] nextpc,
    output reg [31:0]pcf
);

    always @(posedge clk, posedge rst)
    begin
        if(rst)
            pcf<=32'b0;
        else if(~en & pcwrite)
            pcf<=nextpc;
        else
            pcf<=pcf;

    end

endmodule //PC

IM

module IM (
    input [9:0]A,
    output reg [31:0]RD
);

    always @(*) 
  begin
      case(A)//sum=1+2+3+...+100;
      10'd0:RD=32'h20110000;
      10'd1:RD=32'h20100001;
      10'd2:RD=32'h20080065;
      10'd3:RD=32'h12080003;
      10'd4:RD=32'h02308820;
      10'd5:RD=32'h22100001;
      10'd6:RD=32'h08000003;
      10'd7:RD=32'hFE200000;//halt
      default:RD=32'hFC00_0000;
      endcase
  end
endmodule //IM

RF

module RF (
    input clk,
    input rst,
    input [4:0]A1,
    input [4:0]A2,
    input [4:0]A3,
    input signed [31:0]WD3,
    input WE3,
    output wire signed [31:0]RD1,
    output wire signed [31:0]RD2 
);
    reg signed [31:0] RegisterFile [31:0];

    assign RD1=(A1==5'b0)?32'b0:RegisterFile[A1];
    assign RD2=(A2==5'b0)?32'b0:RegisterFile[A2];

    integer i;
    always @(negedge clk,posedge rst) 
    begin
        if(rst)
        begin
            for(i=0;i<32;i=i+1)
            begin
                RegisterFile[i]<=32'b0;
            end
        end
        else
        begin
            if(WE3)
                RegisterFile[A3]<=WD3;
        end
    end



endmodule //RF

ALU

module ALU (
    input signed [31:0] A,
    input signed [31:0] B,
    input [3:0] F,
    output signed [31:0] ALUOutE,
    output Zero,
    output Negtive
);  
    wire signed [31:0] a;
    wire signed [31:0] b;
    wire signed [31:0] BB;
    wire signed [31:0] SI;
    wire signed [31:0] S;
    wire Cout;
    wire signed [31:0] XOR;
    wire signed [31:0] NOR;

    assign BB=(F[2])? (~B):B;
    assign {Cout,S}=A+BB+F[2];

    assign a= A | BB;
    assign b= A & BB;
    assign SI= {31'b0,S[31]};
    assign XOR= A ^ B;
    assign NOR= ~(A | B);

    assign ALUOutE=(F==4'b0000)? b: (F==4'b0001)? a: (F==4'b0010 | F==4'b0110)? S :(F==4'b0111)?{31'b0,Negtive}:(F==4'b0011)?XOR:(F==4'b0110)?NOR:SI;
    assign Negtive=(S[31]==1)?1:0;
    assign Zero=&(~S);

endmodule //ALU

DM

数据存储器一般比较大，会考虑省去复位功能。但是，它在不复位的情况下非常混乱，所以一定要注意先写再读。

module DM (
    input clk,
    input rst,
    input [9:0]A,
    input [31:0]WD,
    input WE,
    output wire signed [31:0] RD
);
    reg [31:0] DataMemory[1023:0];

    assign RD=DataMemory[A];
    integer i=0;

    always @(negedge clk,posedge rst) 
    begin
       /*if(rst)
        begin
            for(i=0;i<1024;i=i+1)
            begin
                DataMemory[i]<=32'b0;
            end
        end*/
        if(WE)
            DataMemory[A]<=WD;
    end

endmodule //DM

有关控制单元，冲突单元的设计处理要根据你设计的流水线能实现哪些指令做出相应的调整，就没办法一一展示啦

---

今天除夕! 大家除夕快乐鸭！！！不多说啦去下板子看流水线效果去了哈哈哈哈