ModelSim2019.4安装

目录

一、下载ModelSim安装包

二、安装ModelSim 

三、安装注册表

四、添加环境变量


一、下载ModelSim安装包

https://www.xiazaila.com/soft/12267.html#downloads

二、安装ModelSim 

1、以管理员身份运行exe文件

2、点击下一步

3、选择安装位置

4、同意许可

5、在桌面创建图表,选择是

6、添加路径,选择是

7、选择否

三、安装注册表

1、在软件安装目录中找到mgls64.dll文件,将只读的号取消

2、将软件安装包里的patch中的MentorKG.exe MGLS.DLL和patch_dll.bat一起拷贝到modelsim安装目录的win32或win64下

3、运行patch_dll.bat,稍等片刻,会生成license文件,将license文件另存为放到安装目录下

四、添加环境变量

1、打开高级系统设置

2、点击环境变量

3、 上面的是用户变量,我们只需要在下面的系统变量添加即可,点击新建,出现对话框

变量名:设置为MGLS_LICENSE_FILE,

变量值:设置为(你存放LICENSE.TXT路径)

4、一直确定即可

Mentor, a Siemens business, has unveiled ModelSim 10.7, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment. About Mentor Graphics ModelSim. Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused. In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code. The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).
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