目录
第121题：Simple FSM 2(asynchronous reset)
第122题：Simple FSM 2(synchronous reset)
第123题：Simple state transitions 3
第124题： Simple one-hot statetransitions 3
第125题：Simple FSM 3(asynchronous reset)
第126题：Simple FSM 3(synchronous reset)
第121题：Simple FSM 2(asynchronous reset)
module top_module
(
input clk ,
input areset , // Asynchronous reset to OFF
input j ,
input k ,
output out
);
parameter OFF=0, ON=1;
reg state, next_state;
always @(*)
begin
// State transition logic
if((state == ON) && (k == 0))
next_state = ON;
else if((state == ON) && (k == 1))
next_state = OFF;
else if((state == OFF) && (j == 0))
next_state = OFF;
else if((state == OFF) && (j == 1))
next_state = ON;
end
always @(posedge clk or posedge areset)
begin
// State flip-flops with asynchronous reset
if(areset)
state <= OFF;
else
state <= next_state;
end
// Output logic
assign out = (state == ON);
endmodule第122题：Simple FSM 2(synchronous reset)
module top_module
(
input clk ,
input reset , // Asynchronous reset to OFF
input j ,
input k ,
output out
);
parameter OFF=0, ON=1;
reg state, next_state;
always @(*)
begin
// State transition logic
if((state == ON) && (k == 0))
next_state = ON;
else if((state == ON) && (k == 1))
next_state = OFF;
else if((state == OFF) && (j == 0))
next_state = OFF;
else if((state == OFF) && (j == 1))
next_state = ON;
end
always @(posedge clk)
begin
// State flip-flops with asynchronous reset
if(reset)
state <= OFF;
else
state <= next_state;
end
// Output logic
assign out = (state == ON);
endmodule第123题：Simple state transitions 3
module top_module
(
input in ,
input [1:0] state ,
output [1:0] next_state ,
output out
);
parameter A=0, B=1, C=2, D=3;
// State transition logic: next_state = f(state, in)
always@(*)
begin
if((state == A)&&(in == 0))
next_state = A;
else if((state == A)&&(in == 1))
next_state = B;
else if((state == B)&&(in == 0))
next_state = C;
else if((state == B)&&(in == 1))
next_state = B;
else if((state == C)&&(in == 0))
next_state = A;
else if((state == C)&&(in == 1))
next_state = D;
else if((state == D)&&(in == 0))
next_state = C;
else if((state == D)&&(in == 1))
next_state = B;
else
next_state = A;
end
// Output logic: out = f(state) for a Moore state machine
assign out = (state == D);
endmodule第124题： Simple one-hot statetransitions 3
module top_module
(
input in ,
input [3:0] state ,
output [3:0] next_state ,
output out
);
parameter A=0, B=1, C=2, D=3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = state[A]&(in==0) | state[C]&(in==0);
assign next_state[B] = state[A]&(in==1) | state[B]&(in==1) | state[D]&(in==1);
assign next_state[C] = state[B]&(in==0) | state[D]&(in==0);
assign next_state[D] = state[C]&(in==1);
// Output logic:
assign out = (state[D]==1);
endmodule第125题：Simple FSM 3(asynchronous reset)
module top_module
(
input clk ,
input in ,
input areset ,
output out
);
parameter A= 0,B= 1,C= 2,D= 3;
reg [3:0] state;
wire [3:0] next_state;
// State transition logic
assign next_state[A] = state[A]&(in==0) | state[C]&(in==0);
assign next_state[B] = state[A]&(in==1) | state[B]&(in==1) | state[D]&(in==1);
assign next_state[C] = state[B]&(in==0) | state[D]&(in==0);
assign next_state[D] = state[C]&(in==1);
// State flip-flops with asynchronous reset
always@(posedge clk or posedge areset)
if(areset)
state <= 4'b0001;
else
state <= next_state;
// Output logic
assign out = state[D]==1;
endmodule第126题：Simple FSM 3(synchronous reset)
module top_module
(
input clk ,
input in ,
input reset ,
output out
);
parameter A= 0,B= 1,C= 2,D= 3;
reg [3:0] state;
wire [3:0] next_state;
// State transition logic
assign next_state[A] = state[A]&(in==0) | state[C]&(in==0);
assign next_state[B] = state[A]&(in==1) | state[B]&(in==1) | state[D]&(in==1);
assign next_state[C] = state[B]&(in==0) | state[D]&(in==0);
assign next_state[D] = state[C]&(in==1);
// State flip-flops with asynchronous reset
always@(posedge clk)
if(reset)
state <= 4'b0001;
else
state <= next_state;
// Output logic
assign out = state[D]==1;
endmodule第127题：Design a Moore FSM
module top_module
(
input clk ,
input reset ,
input [3:1] s ,
output fr3 ,
output fr2 ,
output fr1 ,
output dfr
);
parameter o_s3 = 3'b111,
b_s23= 3'b011,
b_s12= 3'b001,
l_s1 = 3'b000;
reg [2:0] state,next_state;
assign next_state = s;
always@(posedge clk)
if(reset)
state <= l_s1;
else
state <= next_state;
reg r_dfr;
always@(posedge clk)
if(reset)
r_dfr <= 1'b1;
else
r_dfr <= (state == next_state) ? dfr : ((state > next_state)?1'b1:1'b0);
assign fr3= state == l_s1;
assign fr2= state <= b_s12;
assign fr1= state <= b_s23;
assign dfr= r_dfr;
endmodule第128题：Lemmings 1
module top_module
(
input clk ,
input areset , // Freshly brainwashed Lemmings walk left.
input bump_left ,
input bump_right ,
output walk_left ,
output walk_right
);
parameter LEFT=0, RIGHT=1;
reg state, next_state;
always @(*)
begin
if((state == LEFT)&&(bump_left == 1))
next_state = RIGHT;
else if((state == LEFT)&&(bump_left == 0))
next_state = LEFT;
else if((state == RIGHT)&&(bump_right == 1))
next_state = LEFT;
else if((state == RIGHT)&&(bump_right == 0))
next_state = RIGHT;
end
always @(posedge clk or posedge areset)
begin
if(areset)
state <= LEFT;
else
state <= next_state;
end
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
endmodule第129题：Lemmings 2
module top_module
(
input clk ,
input areset , // Freshly brainwashed Lemmings walk left.
input bump_left ,
input bump_right ,
input ground ,
output walk_left ,
output walk_right ,
output aaah
);
parameter LEFT= 0, RIGHT= 1, L_FALL= 2,R_FALL= 3;
reg [1:0] state, next_state;
always @(*)
begin
case(state)
LEFT : if(ground == 1'b0) next_state = L_FALL;
else next_state = bump_left ? RIGHT : LEFT;
RIGHT : if(ground == 1'b0) next_state = R_FALL;
else next_state = bump_right ? LEFT : RIGHT;
L_FALL : if(ground == 1'b0) next_state = L_FALL;
else next_state = LEFT;
R_FALL : if(ground == 1'b0) next_state = R_FALL;
else next_state = RIGHT;
default : state = LEFT;
endcase
end
always@(posedge clk or posedge areset)
begin
if(areset)
state <= LEFT;
else
state <= next_state;
end
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
assign aaah = (state == L_FALL)||(state == R_FALL);
endmodule第130题：Lemmings 3
module top_module
(
input clk ,
input areset , // Freshly brainwashed Lemmings walk left.
input bump_left ,
input bump_right ,
input ground ,
input dig ,
output walk_left ,
output walk_right ,
output aaah ,
output digging
);
parameter LEFT = 3'd0,
RIGHT = 3'd1,
L_FALL = 3'd2,
R_FALL = 3'd3,
L_DIG = 3'd4,
R_DIG = 3'd5;
reg [2:0] state,next_state;
always@(*)
case(state)
LEFT : if(ground == 0) next_state= L_FALL;
else if(dig == 1) next_state= L_DIG;
else if(bump_left == 1) next_state= RIGHT;
else next_state= LEFT;
RIGHT : if(ground == 0) next_state= R_FALL;
else if(dig == 1) next_state= R_DIG;
else if(bump_right == 1) next_state= LEFT;
else next_state= RIGHT;
L_FALL : if(ground == 1) next_state= LEFT;
else next_state= L_FALL;
R_FALL : if(ground == 1) next_state= RIGHT;
else next_state= R_FALL;
L_DIG : if(ground == 0) next_state= L_FALL;
else next_state= L_DIG;
R_DIG : if(ground == 0) next_state= R_FALL;
else next_state= R_DIG;
default : state = LEFT;
endcase
always@(posedge clk or posedge areset)
if(areset)
state <= LEFT;
else
state <= next_state;
assign walk_left = state==LEFT;
assign walk_right = state==RIGHT;
assign aaah = (state==L_FALL) || (state==R_FALL);
assign digging = (state==L_DIG) || (state==R_DIG);
endmodule
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