HDLBits从零开始——第171题到178题答案

最新推荐文章于 2024-09-30 17:34:37 发布

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最新推荐文章于 2024-09-30 17:34:37 发布

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分类专栏： HDLBits 文章标签： fpga开发经验分享学习

本文链接：https://blog.csdn.net/qq_62179548/article/details/130033886

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第171题：Sequential circuit 8

第172题：Sequential circuit 9

第173题：Sequential circuit 10

第171题：Sequential circuit 8

module top_module 
(
    input   clock   ,
    input   a       ,
    output  p       ,
    output  q 
);

always@(negedge clock)
    q <= p;
    
assign  p = clock ? a : p;

endmodule

第172题：Sequential circuit 9

module top_module 
(
    input           clk ,
    input           a   ,
    output  [3:0]   q 
);

always@(posedge clk)
    if(a)
        q <= 4'd4;
    else if(q==4'd6)
        q <= 4'd0;
    else
        q <= q+1'b1;

endmodule

第173题：Sequential circuit 10

module top_module 
(
    input       clk     ,
    input       a       ,
    input       b       ,
    output      q       ,
    output      state  
);

always@(posedge clk)
    if(a==b)
        state <= a;
    else
        state <= state;

assign  q = a==b ? state : ~state;

endmodule

第174题：Clock

`timescale  1ps/1ps
module top_module ( );

reg clk;

initial
    begin
        clk = 0;
    end

always #5   clk = ~clk;

dut dut_inst
( 
    .clk (clk)
) ;

endmodule

第175题：Testbench1

`timescale  1ps/1ps
module top_module ( output reg A, output reg B );

initial
    begin
        A <= 1'b0;
        B <= 1'b0;
        #10
        A <= 1'b1;
        #5
        B <= 1'b1;
        #5
        A <= 1'b0;
        #20
        B <= 1'b0;
    end

endmodule

第176题：AND gate

`timescale 1ps/1ps
module top_module();

reg [1:0]   in;
wire        out;

initial
    begin
        in <= 2'b00;
        #10
        in <= 2'b01;
        #10
        in <= 2'b10;
        #10
        in <= 2'b11;
    end

andgate andgate_inst
(
    .in (in),
    .out(out)
);

endmodule

第177题：Testbench2

`timescale 1ps/1ps
module top_module();

reg         clk ;
reg         in  ;
reg [2:0]   s   ;
wire        out ;

initial
    begin
        clk = 1'b0;
        in <= 1'b0;
        s <= 3'd2;
        #10
        s <= 3'd6;
        #10
        in <= 1'b1;
        s <= 3'd2;
        #10
        in <= 1'b0;
        s <= 3'd7;
        #10
        in <= 1'b1;
        s <= 3'd0;
        #30
        in <= 1'b0;
    end
    
always #5   clk = ~clk;

q7 q7_inst
(
    .clk (clk),
    .in  (in ),
    .s   (s  ),
    .out (out)
);

endmodule

第178题：T flip-flop

`timescale 1ps/1ps
module top_module ();

reg     clk     ;
reg     reset   ;
reg     t       ;
wire    q       ;

initial
    begin
        clk = 1'b0;
        reset <= 1'b1;
        t <= 1'b0;
        #20
        reset <= 1'b0;
        #30
        t <= 1'b1;
    end
    
always #5   clk = ~clk;

tff tff_inst
(
    .clk     (clk  ),    
    .reset   (reset),
    .t       (t    ),
    .q       (q    )
);

endmodule