HDLBits从零开始——第81题到第90题答案

目录

第81题：D flip-flop

第82题：D flip-flops

第83题：DFF with reset

第84题：DFF with reset value

第85题：DFF with asynchronous reset

第86题：DFF with byte enable

第87题：D Latch

第88题：DFF

第89题：DFF

第90题：DFF+gate

---

第81题：D flip-flop

module top_module 
(
    input       clk ,    // Clocks are used in sequential circuits
    input       d   ,
    output reg  q 
);

always@(posedge clk)
    q <= d;

endmodule

第82题：D flip-flops

module top_module 
(
    input           clk ,
    input   [7:0]   d   ,
    output  [7:0]   q
);

always@(posedge clk)
    q <= d;

endmodule

第83题：DFF with reset

module top_module 
(
    input           clk     ,
    input           reset   ,            // Synchronous reset
    input   [7:0]   d       ,
    output  [7:0]   q
);

always@(posedge clk)
    if(reset)
        q <= 0;
    else
        q <= d;

endmodule

第84题：DFF with reset value

module top_module 
(
    input           clk     ,
    input           reset   ,
    input   [7:0]   d       ,
    output  [7:0]   q
);

always@(negedge clk)
    if(reset)
        q <= 8'h34;
    else
        q <= d;

endmodule

第85题：DFF with asynchronous reset

module top_module 
(
    input           clk     ,
    input           areset  ,   // active high asynchronous reset
    input   [7:0]   d       ,
    output  [7:0]   q
);

always@(posedge clk or posedge areset)
    if(areset)
        q <= 0;
    else
        q <= d;

endmodule

第86题：DFF with byte enable

module top_module 
(
    input           clk     ,
    input           resetn  ,
    input   [1:0]   byteena ,
    input   [15:0]  d       ,
    output  [15:0]  q
);

always@(posedge clk)
    if(!resetn)
        q[15:8] <= 0;
    else
        begin
            q[7:0] <= byteena[0]?d[7:0]:q[7:0];
            q[15:8] <= byteena[1]?d[15:8]:q[15:8];
        end

endmodule

第87题：D Latch

module top_module 
(
    input   d   , 
    input   ena ,
    output  q
);

assign  q = ena ? d : q; 

endmodule

第88题：DFF

module top_module 
(
    input       clk ,
    input       d   , 
    input       ar  ,   // asynchronous reset
    output  reg q
);

always@(posedge clk or posedge ar)
    if(ar)
        q <= 0;
    else
        q <= d;

endmodule

第89题：DFF

module top_module 
(
    input       clk ,
    input       d   , 
    input       r   ,   // synchronous reset
    output  reg q
);

always@(posedge clk)
    if(r)
        q <= 0;
    else
        q <= d;

endmodule

第90题：DFF+gate

module top_module 
(
    input       clk ,
    input       in  , 
    output  reg out
);

always@(posedge clk)
    out <= in^out;

endmodule