STM32 FSMC总线深入研究
由于CPU与FPGA通信的需要,以及对8080总线的熟悉,首选采用了STM32的FSMC总线,作为片间通信接口。FSMC能达到16MHz的写入速度,理论上能写20fps的1024*768的图片哈哈。(当然实际上是不可能的,就算是DMA传输,数据源也跟不上,实际上刷模拟的图片每秒10fps,刷的很high)当然这不是本篇的要点,这里主要研究STM32的FSMC接口,将速度提升到极限。
1. FSMC协议分析
如下为ILI9325的8080接口的协议
CS(片选信号):低电平片选有效,高电平失能(默认为高:失能)
RS(数据寄存器):低电平写寄存器,高电平写数据(默认为高:写数据)FSMC默认为低。。。。
RD(读信号) :低电平有效,上升沿写入数据,高电平失能(默认为高,失能)
WR(写信号) :低电平有效,上升沿写入数据,高电平失能(默认为高,失能)
FSMC写SRAM模式如下:
(1)读操作
(2)写操作
HCLK为系统时钟72MHz
综上,分析出FSMC与8080接口协议异同点
(1)同:CS,RS,RD有效电平都一样,单个字节的写入与读取时序完全一样
(2)异:
A:8080 默认RS为高,而FSMC默认RS为低
B:8080接口协议能保持CS,RS等有效,连续写数据,而FSMC以此只能输出一个数据。
C:8080协议没有地址线,而FSMC还有地址线,这使得数据输出不连续。
2. FSMC时序研究
下图为FSMC写命令与数据的时序图,从中根据上图可以分析出FSMC可以实现16M的数据写入。FSMC的信号线翻转非常快,这使得IC或者FPGA时序设计上得非常严谨。FSMC最大实现了72MHz(66.7到100MHz之间,实际为72MHz,HCLK)的翻转速度,这要求外部器件支持那么高的速率。
寄存器配置(寄存器+数据)
连续数据写入(0xBB:写数据开始),命令后,RS默认拉低(FSMC和标准不一样的地方)
数据建立很快
写数据,然后默认RS拉低
整体的时序可模拟为:
task task_writecmd;
input [15:0] cmd;
begin
mcu_cs = 0;
mcu_rs = 0;
mcu_data = cmd;
#20;
mcu_we = 0;
#20;
mcu_we = 1;
#15;
mcu_rs = 1;
mcu_cs = 1;
#20;
end
endtask
task task_writedata;
input [15:0] data;
begin
mcu_cs = 0;
mcu_rs = 1;
mcu_data = data;
#20;
mcu_we = 0;
#20;
mcu_we = 1;
#15;
mcu_rs = 1;
mcu_cs = 1;
#20;
end
endtask
3. FSMC接口初始化
根据手册,相关参数如下表所示。这里我发现所谓最小值还能设置为最小,但实际速度差不多。FSMC协议时间参数如下所示:
有人跟我说,手册是保守的;有人跟我说,在小就是默认值了。我不太理解。感觉速度每提升,应该在小就是默认了。不过,反正我追求速度的极限。
以下是FSMC-SRAM模式下的初始化代码,分享的同时,希望对你有用。
<span class="rem">/* Private typedef -----------------------------------------------------------*/</span>
typedef <span class="kwrd">struct</span>
{
vu16 LCD_REG;
vu16 LCD_RAM;
} LCD_TypeDef;
<span class="preproc">#define</span> LCD_WriteCmd(cmd) LCD->LCD_REG = cmd
<span class="preproc">#define</span> LCD_WriteData(data) LCD->LCD_RAM = data
<span class="rem">/* LCD is connected to the FSMC_Bank1_NOR/SRAM4 and NE4 is used as ship select signal */</span>
<span class="preproc">#define</span> LCD_BASE ((u32)(0x60000000 | 0x0C000000))
<span class="preproc">#define</span> LCD ((LCD_TypeDef *) LCD_BASE)
<span class="kwrd">void</span> LCD_FSMCConfig(<span class="kwrd">void</span>)
{
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
FSMC_NORSRAMTimingInitTypeDef p;
<span class="rem">/*-- FSMC Configuration ------------------------------------------------------*/</span>
<span class="rem">/*----------------------- SRAM Bank 4 ----------------------------------------*/</span>
<span class="rem">/* FSMC_Bank1_NORSRAM4 configuration */</span>
<span class="rem">//标准</span>
<span class="rem">// p.FSMC_AddressSetupTime = 1;</span>
<span class="rem">// p.FSMC_AddressHoldTime = 2;</span>
<span class="rem">// p.FSMC_DataSetupTime = 2; </span>
<span class="rem">// p.FSMC_BusTurnAroundDuration = 1;</span>
<span class="rem">// p.FSMC_CLKDivision = 1;</span>
<span class="rem">// p.FSMC_DataLatency = 2;</span>
<span class="rem">//超快</span>
p.FSMC_AddressSetupTime = 0;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 1;
p.FSMC_BusTurnAroundDuration = 0;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
<span class="rem">/* Color LCD configuration ------------------------------------</span>
<span class="rem"> LCD configured as follow:</span>
<span class="rem"> - Data/Address MUX = Disable</span>
<span class="rem"> - Memory Type = SRAM</span>
<span class="rem"> - Data Width = 16bit</span>
<span class="rem"> - Write Operation = Enable</span>
<span class="rem"> - Extended Mode = Enable</span>
<span class="rem"> - Asynchronous Wait = Disable */</span>
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; <span class="rem">//2.0</span>
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
<span class="rem">/* BANK 4 (of NOR/SRAM Bank 1~4) is enabled */</span>
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
}
原文:
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