插入clock gate之后FV失败的问题
相关变量:verification_clock_gate_hold_mode
在默认情况下,fm认为增添了门控插入(综合时)和之前没有门控的RTL的寄存器是不相等的 也就是说,如果综合时,使用了命令进行了门控插入,那么在形式验证时,就需要设置相应的verification_clock_gate_hold_mode.
user guide上面说这个可以设置成几个值,
* “none” - does not consider clock-gated flip-flop states equivalent to non-clock-gated flip-flop states (the default).
* “low” - considers latch-based clock gating, and combinational clock gating that holds the clock low when inactive (or high for falling-edge-triggered flip-flops).
* “high” - considers combinational clock gating that holds the clock high when inactive (or low for falling-edge-triggered flip-flops).
* “any” - considers both “high” and “low” styles of clock gating within the same design.
clock gating 应该就是只有两种形式的gating:
AND gate
OR gate