去掉前三行和后两列
`timescale 1ns / 1ps
// Company:
// Engineer:
//
// Create Date: 19:34:30 09/12/2016
// Design Name: top_module
// Module Name: D:/SIFT/project/tb_Gaussian_gray/tp_top_test.v
// Project Name: tb_Gaussian_gray
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
module tp_top_test;
parameter size = 4096;
// Inputs
reg CLK;
reg nRESET;
// reg [7:0] PIXEL_IN;
// reg VALID_IN;
// Outputs
reg [7:0] data_out;
reg [7:0]image_b[0:size-1];
integer read_image_point;
integer image_point;
reg [12:0] write_addr;
integer write_text_point;
// Instantiate the Unit Under Test (UUT)
// top_module uut (
// .CLK(CLK),
// .nRESET(nRESET),
// .PIXEL_IN(PIXEL_IN),
// .VALID_IN(VALID_IN),
// .PIXEL_OUT(PIXEL_OUT)
// );
initial begin