信号延迟一个单位

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    09:57:16 07/19/2017 
// Design Name: 
// Module Name:    histogram 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module histogram(
	LVAL,
	data,
	CLK,
	nRESET
    );

	input [7:0]data;
	input CLK,nRESET;
	
	input LVAL;
	
	reg LVAL_temp1,LVAL_temp2;    
	reg [7:0]data_temp1,data_temp2;

	always @(posedge CLK or negedge nRESET)
	begin
		if(!nRESET) 
		begin
		  {LVAL_temp2,LVAL_temp1}<=2'd0;
		  {data_temp2,data_temp1}<=16'd0;
		end 
		
		else 
		begin
		  {LVAL_temp2,LVAL_temp1}<={LVAL_temp1,LVAL};
		  {data_temp2,data_temp1}<={data_temp1,data};
		end
	end

endmodule