MAX7219驱动数码管的代码,C语言有大把的代码参考,实现的原理这里我就不细说了,其他博主说得很详细,但是Verilog的代码并没有很多,因此,这里我封装好了代码,仅需根据自己的需要去配置就可以
module nixie_tude(
input sys_clk , //系统时钟
input sys_rst_n, //系统复位,低电平有效
input wire [3:0] switch_1,
input wire [3:0] switch_2,
input wire [3:0] switch_3,
input wire [3:0] switch_4,
input wire [3:0] switch_5,
input wire [3:0] switch_6,
input wire [3:0] switch_7,
input wire [3:0] switch_8,
output reg o_cs, //片选
output reg o_clk, //时钟
output reg o_din //数据
);
reg [31:0] counter; //计数器
reg [7:0] spi_state; //状态标志
reg [15:0] data; //数据
reg [7:0] flag; //数据标志
reg [7:0] switch_1_q;
reg [7:0] switch_2_q;
reg [7:0] switch_3_q;
reg [7:0] switch_4_q;
reg [7:0] switch_5_q;
reg [7:0] switch_6_q;
reg [7:0] switch_7_q;
reg [7:0] switch_8_q;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(!sys_rst_n)begin
switch_1_q <= 8'h00;
switch_2_q <= 8'h00;
switch_3_q <= 8'h00;
switch_4_q <= 8'h00;
switch_5_q <= 8'h00;
switch_6_q <= 8'h00;
switch_7_q <= 8'h00;
switch_8_q <= 8'h00;
end
else
begin
case(switch_1)
4'h0 : switch_1_q <= 8'h7e;
4'h1 : switch_1_q <= 8'h30;
4'h2 : switch_1_q <= 8'h6d;
4'h3 : switch_1_q <= 8'h79;
4'h4 : switch_1_q <= 8'h33;
4'h5 : switch_1_q <= 8'h5b;
4'h6 : switch_1_q <= 8'h5f;
4'h7 : switch_1_q <= 8'h70;
4'h8 : switch_1_q <= 8'h7f;
4'h9 : switch_1_q <= 8'h7b;
4'ha : switch_1_q <= 8'h77;
4'hb : switch_1_q <= 8'h1f;
4'hc : switch_1_q <= 8'h4e;
4'hd : switch_1_q <= 8'h3d;
4'he : switch_1_q <= 8'h4f;
4'hf : switch_1_q <= 8'h47;
endcase
case(switch_2)
4'h0 : switch_2_q <= 8'h7e;
4'h1 : switch_2_q <= 8'h30;
4'h2 : switch_2_q <= 8'h6d;
4'h3 : switch_2_q <= 8'h79;
4'h4 : switch_2_q <= 8'h33;
4'h5 : switch_2_q <= 8'h5b;
4'h6 : switch_2_q <= 8'h5f;
4'h7 : switch_2_q <= 8'h70;
4'h8 : switch_2_q <= 8'h7f;
4'h9 : switch_2_q <= 8'h7b;
4'ha : switch_2_q <= 8'h77;
4'hb : switch_2_q <= 8'h1f;
4'hc : switch_2_q <= 8'h4e;
4'hd : switch_2_q <= 8'h3d;
4'he : switch_2_q <= 8'h4f;
4'hf : switch_2_q <= 8'h47;
endcase
case(switch_3)
4'h0 : switch_3_q <= 8'h7e;
4'h1 : switch_3_q <= 8'h30;
4'h2 : switch_3_q <= 8'h6d;
4'h3 : switch_3_q <= 8'h79;
4'h4 : switch_3_q <= 8'h33;
4'h5 : switch_3_q <= 8'h5b;
4'h6 : switch_3_q <= 8'h5f;
4'h7 : switch_3_q <= 8'h70;
4'h8 : switch_3_q <= 8'h7f;
4'h9 : switch_3_q <= 8'h7b;
4'ha : switch_3_q <= 8'h77;
4'hb : switch_3_q <= 8'h1f;
4'hc : switch_3_q <= 8'h4e;
4'hd : switch_3_q <= 8'h3d;
4'he : switch_3_q <= 8'h4f;
4'hf : switch_3_q <= 8'h47;
endcase
case(switch_4)
4'h0 : switch_4_q <= 8'h7e;
4'h1 : switch_4_q <= 8'h30;
4'h2 : switch_4_q <= 8'h6d;
4'h3 : switch_4_q <= 8'h79;
4'h4 : switch_4_q <= 8'h33;
4'h5 : switch_4_q <= 8'h5b;
4'h6 : switch_4_q <= 8'h5f;
4'h7 : switch_4_q <= 8'h70;
4'h8 : switch_4_q <= 8'h7f;
4'h9 : switch_4_q <= 8'h7b;
4'ha : switch_4_q <= 8'h77;
4'hb : switch_4_q <= 8'h1f;
4'hc : switch_4_q <= 8'h4e;
4'hd : switch_4_q <= 8'h3d;
4'he : switch_4_q <= 8'h4f;
4'hf : switch_4_q <= 8'h47;
endcase
case(switch_5)
4'h0 : switch_5_q <= 8'h7e;
4'h1 : switch_5_q <= 8'h30;
4'h2 : switch_5_q <= 8'h6d;
4'h3 : switch_5_q <= 8'h79;
4'h4 : switch_5_q <= 8'h33;
4'h5 : switch_5_q <= 8'h5b;
4'h6 : switch_5_q <= 8'h5f;
4'h7 : switch_5_q <= 8'h70;
4'h8 : switch_5_q <= 8'h7f;
4'h9 : switch_5_q <= 8'h7b;
4'ha : switch_5_q <= 8'h77;
4'hb : switch_5_q <= 8'h1f;
4'hc : switch_5_q <= 8'h4e;
4'hd : switch_5_q <= 8'h3d;
4'he : switch_5_q <= 8'h4f;
4'hf : switch_5_q <= 8'h47;
endcase
case(switch_6)
4'h0 : switch_6_q <= 8'h7e;
4'h1 : switch_6_q <= 8'h30;
4'h2 : switch_6_q <= 8'h6d;
4'h3 : switch_6_q <= 8'h79;
4'h4 : switch_6_q <= 8'h33;
4'h5 : switch_6_q <= 8'h5b;
4'h6 : switch_6_q <= 8'h5f;
4'h7 : switch_6_q <= 8'h70;
4'h8 : switch_6_q <= 8'h7f;
4'h9 : switch_6_q <= 8'h7b;
4'ha : switch_6_q <= 8'h77;
4'hb : switch_6_q <= 8'h1f;
4'hc : switch_6_q <= 8'h4e;
4'hd : switch_6_q <= 8'h3d;
4'he : switch_6_q <= 8'h4f;
4'hf : switch_6_q <= 8'h47;
endcase
case(switch_7)
4'h0 : switch_7_q <= 8'h7e;
4'h1 : switch_7_q <= 8'h30;
4'h2 : switch_7_q <= 8'h6d;
4'h3 : switch_7_q <= 8'h79;
4'h4 : switch_7_q <= 8'h33;
4'h5 : switch_7_q <= 8'h5b;
4'h6 : switch_7_q <= 8'h5f;
4'h7 : switch_7_q <= 8'h70;
4'h8 : switch_7_q <= 8'h7f;
4'h9 : switch_7_q <= 8'h7b;
4'ha : switch_7_q <= 8'h77;
4'hb : switch_7_q <= 8'h1f;
4'hc : switch_7_q <= 8'h4e;
4'hd : switch_7_q <= 8'h3d;
4'he : switch_7_q <= 8'h4f;
4'hf : switch_7_q <= 8'h47;
endcase
case(switch_8)
4'h0 : switch_8_q <= 8'h7e;
4'h1 : switch_8_q <= 8'h30;
4'h2 : switch_8_q <= 8'h6d;
4'h3 : switch_8_q <= 8'h79;
4'h4 : switch_8_q <= 8'h33;
4'h5 : switch_8_q <= 8'h5b;
4'h6 : switch_8_q <= 8'h5f;
4'h7 : switch_8_q <= 8'h70;
4'h8 : switch_8_q <= 8'h7f;
4'h9 : switch_8_q <= 8'h7b;
4'ha : switch_8_q <= 8'h77;
4'hb : switch_8_q <= 8'h1f;
4'hc : switch_8_q <= 8'h4e;
4'hd : switch_8_q <= 8'h3d;
4'he : switch_8_q <= 8'h4f;
4'hf : switch_8_q <= 8'h47;
endcase
end
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if(!sys_rst_n)begin
o_cs <= 1'b1;
o_clk <= 1'b0;
o_din <= 1'b0;
spi_state <= 7'd0;
data <= 16'hffff;
flag <= 7'd0;
counter <= 32'd0;
end
else begin
//
if(spi_state == 7'd0)begin
if(flag == 7'd0)
data <= 16'h0900;
else if(flag == 7'd1)
data <= 16'h0a03;
else if(flag == 7'd2)
data <= 16'h0b07;
else if(flag == 7'd3)
data <= 16'h0c01;
else if(flag == 7'd4)
data <= 16'h0f00;
else if(flag == 7'd5)
data <= ((16'h01<<8)+ switch_1_q);
else if(flag == 7'd6)
data <= ((16'h02<<8)+ switch_2_q);
else if(flag == 7'd7)
data <= ((16'h03<<8)+ switch_3_q);
else if(flag == 7'd8)
data <= ((16'h04<<8)+ switch_4_q);
else if(flag == 7'd9)
data <= ((16'h05<<8)+ switch_5_q);
else if(flag == 7'd10)
data <= ((16'h06<<8)+ switch_6_q);
else if(flag == 7'd11)
data <= ((16'h07<<8)+ switch_7_q);
else if(flag == 7'd12)
data <= ((16'h08<<8)+ switch_8_q);
if(counter==32'd1000)begin
o_cs <= 1'b0;
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd1)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
//
else if(spi_state == 7'd2)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd3)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd4)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd5)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd6)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd7)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd8)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd9)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd10)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd11)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd12)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd13)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd14)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd15)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd16)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd17)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd18)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd19)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd20)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd21)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd22)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd23)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd24)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd25)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd26)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd27)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd28)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd29)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd30)begin
if(counter==32'd1000)begin
o_clk <= 1'b0;
if((data & 16'h8000)>>15)
o_din <= 1'b1;
else
o_din <= 1'b0;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd31)begin
if(counter==32'd1000)begin
o_clk <= 1'b1;
data <= data * 2;
spi_state <= spi_state + 7'd1;
counter <= 32'd0;
end
else
begin
counter <= counter + 1'b1;
end
end
else if(spi_state == 7'd32)begin
o_cs <= 1'b1;
data <= 16'hffff;
if(flag < 8'd12)
flag <= flag + 1'b1;
else
flag <= 1'b0;
spi_state <= 7'd0;
end
end
end
endmodule