Designing_With_EZ-USB_FX2LP_Slave_FIFO_Interface-Source Code_Verilog——Stream Out

（1）fx2lp_slaveFIFO2b_streamOUT_fpga_top.v

module fx2lp_slaveFIFO2b_streamOUT_fpga_top(
	fdata,                                //  FIFO data lines.
        faddr,                                //  FIFO select line
        slrd,                                 //  Read control lin
        slwr,                                 //  Write control li
        sloe,                                 //  Slave Output Enable control
        flagd,                                //  EP6 full flag
        flaga,                                //  EP2 empty flag
	done,
        clk,                                   //  Interface Clock
	clk_out,
	pkt_end
);

inout [15:0]fdata;
input flaga;
input flagd;
input clk;

output [1:0]faddr;
output sloe;
output slwr;
output slrd;
output pkt_end;
output clk_out;
output done;

reg slrd_n;
reg slwr_n;
reg sloe_n;

wire [15:0] data_out;

wire clk_out_0;
wire clk_out_90;
wire clk_out_180;
wir