Advanced Programmable Interrupt Controller
xApic = APIC
x2APIC is the most recent generation of the Intel programmable interrupt controller, introduced with the Nehalem microarchitecture.
1. 增加cpu数量支持,原先256个, 现在2^32个。
The x2APIC now uses 32 bits to address CPUs, allowing to address up to 2^32-1 CPUs using the physical destination mode. The logical destination mode now works differently and introduces clusters. Using this mode, one can address up to 2^20-16 processors.
2:减少ipi中断
The improved interface reduces the number of needed APIC register access for sending Inter-processor interrupts.
3: 和apic兼容The x2APIC architecture also provides backward compatibility modes to the original Intel APIC Architecture (introduced with the Pentium/P6) and with the xAPICarchitecture (introduced with the Pentium 4).