x86 Architecture
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cache Coherency
What Does Coherency Mean?Informally: – Any read must return the most recent write– Too strict and very difficult to implement • Better: – Any write must eventually be seen by a read– All w转载 2013-08-02 10:00:31 · 657 阅读 · 0 评论 -
qemu code
qemu init pc_piix.c (G:\code\qemu-1.6.1\hw\i386):machine_init(pc_machine_init);machine_init(pc_machine_init); pc_machine_init pc_i440fx_machine_v1_6 pc_init_pci_1_6 pc_init_pci原创 2013-10-15 14:19:40 · 2176 阅读 · 0 评论 -
ibm developerworks
http://www.ibm.com/developerworks/cn/views/linux/libraryview.jsphttp://www.ibm.com/developerworks/cn/views/linux/libraryview.jsp?end_no=100&lcl_sort_order=asc&type_by=%E6%89%80%E6%9C%89%E7%B1%BB原创 2013-07-12 09:48:46 · 979 阅读 · 0 评论 -
cache 计算关系
cache 计算关系1: 地址以32位为例分为 32 = H + M + L (high + middle + low)假设 E = 12:全部 2^32 地址,映射到 2^(32-H) 的地址空间也就是说后 M+L = 32-H 位相同的地址,都会映射到同一个cache Line中那么如果2个地址的后 M+L 位相同,并且反复使用,则会反复切换出来出去,效原创 2013-11-12 16:09:15 · 1618 阅读 · 0 评论 -
aaa
http://www.it.uu.se/edu/course/homepage/hpb/vt12/http://www.cs.ucla.edu/~pouchet/doc/taco-slides.12.pdfhttp://www.usatlas.bnl.gov/~fisyak/star/Presentations/TrackingWorkShopFrankfurt/V原创 2013-11-08 00:02:39 · 692 阅读 · 0 评论 -
单片机
单片机内写汇编实现某些基本功能遥控器原创 2013-11-13 11:15:33 · 846 阅读 · 0 评论 -
总线
关于PCI总线了解这些设备,无非是了解其各种寄存器的使用。对于PCI,无非是了解configuration space的各种寄存器的意义。为了省力,总是去百度搜索,google搜索,搜索到各种垃圾文章,一些低手,菜鸟写的文章。结果越看越不懂。而且感到畏惧,认为很难。其实大师设计的东西,都是结构清晰,简单清晰的。所谓unix哲学,就是大道至简。最简答的办法,最直接的办法,实现原创 2014-03-10 15:15:32 · 593 阅读 · 0 评论 -
EEPROM and FLASH
ROM在微机的发展初期,BIOS都存放在ROM(Read Only Memory,只读存储器)中。ROM内部的资料是在ROM的制造工序中,在工厂里用特殊的方法被烧录进去的,其中的内容只能读不能改,一旦烧录进去,用户只能验证写入的资料是否正确,不能再作任何修改。如果发现资料有任何错误,则只有舍弃不用,重新订做一份。ROM是在生产线上生产的,由于成本高,一般只用在大批量应用的场合。原创 2014-04-03 16:40:35 · 1070 阅读 · 0 评论 -
Introduction to Flash Memory -- It is used more as a hard drive than as RAM.
Speed: RAM >> FLASH >> Hard Drive Physical mechanical : FLASH: electronic , no mechanical parts, 20% of the power, one hundred times faster than traditional mechanical hard原创 2014-04-04 09:39:03 · 805 阅读 · 0 评论 -
operand order in x86 assembly language
order in x86 assembly languageADD—AddOpcode Instruction Op/En 64-bit Mode Compat/Leg Mode Description04 ib ADD AL, imm8 I Valid Valid Add imm8 to AL.05 iw ADD AX, im原创 2014-05-05 10:27:51 · 763 阅读 · 0 评论 -
三级页表
4.3 32-BIT PAGING0: CR3(12-31) --> PD page addressCR3(12-31) x 4K --> PD physical address 1: (PD physical address + level1 offset)(12-31) --> PT page address(PD physical address + le原创 2014-09-19 12:02:19 · 3496 阅读 · 0 评论 -
APIC Timer
apicTimerInit#define APIC_REG_TIMER 0x320/* LVT (Timer) */#define APIC_REG_TIMER_ICR 0x380/* Timer Initial Count Reg */#define APIC_REG_TIMER_CCR 0x390/* Timer Current Count Re原创 2014-09-19 17:00:43 · 1320 阅读 · 0 评论 -
x86-64模式
传统模式(Legacy Mode)这种模式是为了令64位Xeon能没有障碍地执行现有的32位和16位程序而设计的,实际上就是32位x86时代的IA-32模式,此时现有x86程序无需作任何的改变,和我们目前使用着的32位环境一模一样。因为Nacona Xeon的核心仍然是沿着32位设计的,所以这个模式只是把所有为64位计算而新增的运算机制都屏蔽起来。兼容模式(Compatibilit原创 2014-09-20 22:42:37 · 1280 阅读 · 0 评论 -
xapic , x2apic
Advanced Programmable Interrupt ControllerxApic原创 2014-09-21 00:58:55 · 4967 阅读 · 0 评论 -
EPT 原理解释
EPTWhen EPT is in use, certain addresses that would normally be treated as physical addresses (and used to access memory) are instead treated as guest-physical addresses. Guest-physical原创 2014-08-28 12:22:18 · 2630 阅读 · 0 评论 -
8.3 SERIALIZING INSTRUCTIONS
The Intel 64 and IA-32 architectures define several serializing instructions. These instructions force the processor to complete all modifications to flags, registers, and memory by previous instruc原创 2013-09-26 15:57:52 · 1089 阅读 · 0 评论 -
System V Application Binary Interface AMD64 Architecture Processor Supplement
Passing Once arguments are classified, the registers get assigned (in left-to-rightorder) for passing as follows:1. If the class is MEMORY, pass the argument on the stack.2. If the class is INT原创 2013-09-26 14:29:46 · 1149 阅读 · 0 评论 -
rep movs loads stos
repOperationIF AddressSize = 16 THEN Use CX for CountReg; Implicit Source/Dest operand for memory use of SI/DI; ELSE IF AddressSize = 64 THEN Use RCX for CountReg;原创 2013-09-16 13:11:40 · 936 阅读 · 0 评论 -
内存 cache
Introduction to Caches cache slot 的数据结构SlotsLet's get into more specific details about the cache. In particular, we'll describe an individual slot.A slot consists of the following:转载 2013-08-05 11:43:43 · 995 阅读 · 0 评论 -
CPU Switches from Kernel mode to User Mode on X86 : When and How?
详解转载 2013-08-06 11:10:40 · 2069 阅读 · 0 评论 -
CHAPTER 29 APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
CHAPTER 29 APIC VIRTUALIZATION AND VIRTUAL INTERRUPTSObject:The VMCS includes controls that enable the virtualization of interrupts and the Advanced Programmable Interrupt Controller (APIC).原创 2013-08-19 10:38:42 · 1093 阅读 · 0 评论 -
CHAPTER 29 APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
CHAPTER 29 APIC VIRTUALIZATION AND VIRTUAL INTERRUPTSObject:The VMCS includes controls that enable the virtualization of interrupts and the Advanced Programmable Interrupt Controller (APIC).原创 2013-08-19 16:49:17 · 1416 阅读 · 0 评论 -
MSI
从各处转载,算是原创吧。谢谢原作者。From: http://blog.sina.com.cn/s/blog_6472c4cc0100qxc6.html3.3.2 处理器到PCI处理器到PCI设备的数据传送下文以图3‑2所示的处理器系统为例,说明处理器向PCI设备11进行存储器写的数据传送过程。处理器向PCI设备进行读过程与写过程略有区别,因为存储器写使用P原创 2013-08-21 11:47:29 · 1899 阅读 · 0 评论 -
what-is-the-bios-and-what-does-it-do
BIOShttp://forum-en.msi.com/faq/article/what-is-the-bios-and-what-does-it-do原创 2013-08-20 23:30:30 · 911 阅读 · 0 评论 -
LKA linux kernel architechture
一本好书就是一个好老师,好师傅,好朋友。LKA就是一本这样的书。1: OS概念,层次2:怎么阅读代码,抓住重点3:翻译,英文学习原创 2013-08-09 16:26:27 · 783 阅读 · 0 评论 -
mit 6.828
http://pdos.csail.mit.edu/6.828/2012/index.html转载 2013-08-12 22:56:23 · 885 阅读 · 0 评论 -
VT-d
从VT-x到VT-d Intel虚拟化技术发展蓝图第1页:Intel虚拟化发展蓝图第2页:x86处理器虚拟化难题:Ring Privi..第3页:x86处理器虚拟化难题解决:Intel ..第4页:新的问题:I/O设备虚拟化第5页:I/O设备虚拟化问题的解决:Intel ..转载 2013-08-26 09:55:12 · 1546 阅读 · 0 评论 -
What exactly do shadow page tables (for VMMs) do
Shadow page tablesShadow page tables are used by the hypervisor to keep track of the state in which the guest "thinks" its page tables should be. The guest can't be allowed access to the har转载 2013-08-16 15:41:47 · 1390 阅读 · 0 评论 -
Hardware Virtualization: the Nuts and Bolts / EPT / VPID
http://www.anandtech.com/show/2480very Good !转载 2013-08-16 16:02:46 · 1589 阅读 · 0 评论 -
Linux 虚拟化技术
虚拟化技术漫谈http://www.ibm.com/developerworks/cn/linux/l-cn-vt/index.html虚拟 Linuxhttp://www.ibm.com/developerworks/cn/linux/l-linuxvirt/index.html转载 2013-08-14 15:57:02 · 665 阅读 · 0 评论 -
CHAPTER 24 VIRTUAL-MACHINE CONTROL STRUCTURES
24.4 GUEST-STATE AREA 24.4.1 Guest Register State Control registers CR0, CR3, and CR4 Debug register DR7 RSP, RIP, and RFLAGS CS, SS, DS, ES, FS, GS, LDTR,原创 2013-08-16 13:46:03 · 1491 阅读 · 0 评论 -
VMX NON-ROOT OPERATION && VM ENTRIES && VMX SUPPORT FOR ADDRESS TRANSLATION
CHAPTER 25 VMX NON-ROOT OPERATION25.3 CHANGES TO INSTRUCTION BEHAVIOR IN VMX NON-ROOT OPERATION• MOV from CR3. If the “enable EPT” VM-execution control is 1 and an execution of MOV from C原创 2013-08-16 15:35:43 · 1472 阅读 · 0 评论 -
MP Initialization Protocol Algorithm for Intel Xeon Processors
8.4.3 MP Initialization Protocol Algorithm for Intel Xeon Processors原创 2014-09-18 15:48:34 · 1012 阅读 · 0 评论