//设计一个自动饮料售卖机,共有两种饮料,其中饮料 A 每个 10 分钱,饮料 B 每个 5 分钱
//硬币有 5 分和 10 分两种,并考虑找零。
//要求用状态机实现,定义状态,画出状态转移图,并用 Verilog 完整描述该识别模块。
//sel为1.表示选择饮料A,sel为0,表示选择饮料B。
//输入2’b01–表示5分钱,2’b10–表示10分钱。
//d_in表示投入钱的数量,d_out高表示输出饮料,d_c表示找零。
module sel_fsm (clk,rst,sel,din,dout,dc);
input clk,rst,sel;
input [1:0] din;
output reg dout;
output reg [1:0] dc;
reg [1:0] state,nstate;
parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10;
always @ (posedge clk or negedge rst) begin
if(!rst)
state <= s0;
else
state <= nstate;
end
always @ (*) begin
case(state)
s0:begin
if(din == 2'b01 && sel == 1'b1) begin
nstate = s1;
{dc,dout} = 3'b000;
end
else if(din == 2'b10 && sel == 1'b1) begin
nstate = s0;
{dc,dout} = 3'b001;
end
else if(din == 2'b01 && sel == 1'b0) begin
nstate = s0;
{dc,dout} = 3'b001;
end
else if(din == 2'b10 && sel == 1'b0) begin
nstate = s1;
{dc,dout} = 3'b011;
end
else begin
nstate = s0;
{dc,dout} = 3'b000;
end
end
s1:begin
if(din == 2'b01 && sel == 1'b1) begin
nstate = s0;
{dc,dout} = 3'b001;
end
else if(din == 2'b10 && sel == 1'b1) begin
nstate = s1;
{dc,dout} = 3'b011;
end
else if(sel == 1'b0) begin
nstate = s0;
{dc,dout} = 3'b001;
end
else begin
nstate = s1;
end
end
default: nstate = s0;
endcase
end
endmodule
测试代码
```cpp
`timescale 1ns/100ps
module sel_fsm_tb;
reg clk,rst,sel;
reg [1:0] din;
wire dout;
wire [1:0] dc;
sel_fsm n1 (clk,rst,sel,din,dout,dc);
initial begin
clk = 0;
rst = 0;
#10 rst = 1;
end
always begin
#10 clk = ~clk;
end
initial begin
#10 sel = 1;
din = 2'b01;
#10 din = 2'b01;
#10 din = 2'b01;
#10 din = 2'b10;
#10 din = 2'b10;
#10 din = 2'b00;
#10 sel = 0;
#10 din = 2'b00;
#10 din = 2'b01;
#10 din = 2'b10;
#10 din = 2'b10;
end
endmodule
波形图:
参考文章:https://www.cnblogs.com/shadow-fish/p/13543519.html