chapter2 Cyclone Architecture的翻译1

最新推荐文章于 2024-09-23 18:27:17 发布

stormjason

最新推荐文章于 2024-09-23 18:27:17 发布

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分类专栏： FPGA 文章标签： LAB

本文链接：https://blog.csdn.net/stormjason/article/details/73456544

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Cyclone器件采用二维架构，由LABs和嵌入式内存块组成，通过可变速度的列和行互连进行信号连接。每个LAB包含10个LE，用于高效实现用户逻辑功能。设备范围从2,910到20,060个LE。LABs使用行时钟和局部互连生成控制信号，LE则能实现加法器和减法器功能，优化逻辑性能。" 109208069,9806832,CAP理论与kafka的一致性实现,"['分布式系统', '数据库理论', '消息队列', 'kafka']

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功能描述

Cyclone® devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks.

Cyclone®器件包含二维行和列架构来实现自定义逻辑。可变速度的列和行互连提供LAB和嵌入式内存块的信号互连。

The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. Cyclone devices range between 2,910 to 20,060 LEs.

逻辑阵列由LAB组成，每个LAB中有10个LE。一个LE是逻辑的小单元提供用户逻辑的有效实现
功能。 LAB在设备上分组成行和列。Cyclone器件的范围在2,910到20,060 LE之间。

M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 250 MHz. These blocks are grouped into columns across the device in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of embedded RAM.

M4K RAM块是具有4K位的真正的双端口存储器块内存加奇偶校验（4,608位）。这些块提供专门的真实双端口，简单的双端口或高达36位宽的单端口内存高达250 MHz。这些块在设备上分组成列在某些LAB之间。 Cyclone器件提供60到288 Kbits之间嵌入式RAM。

Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the ends of LAB rows and columns around the periphery of the device. I/O pins support various single-ended and differential I/O standards, such as the 66- and 33-MHz, 64- and 32-bit PCI standard and the LVDS I/O standard at up to 640 Mbps. Each IOE contains a bidire