1.简单计数器

HDL-实验（1）

module counter(
CLK,
RST,
CNT);


input CLK,RST;
output  [3:0] CNT;

reg[3:0] CNTMax=6;
reg[3:0]  CNT;

always @ (posedge CLK or posedge RST)
begin
if (RST)
CNT <= 0;
else if(CNT < CNTMax)
CNT <= CNT+1'b1;
else if(CNT >= CNTMax)
begin
CNT <= 0;
if(CNTMax <9)
CNTMax <=CNTMax+1'b1;
else
CNTMax <=6 ;
end
end
endmodule