Android系统proc下查看cpuinfo的参数信息

一、命令 adb shell cat /proc/cpuinfo

我的脚本 Cpuinfo.bat，目的手机系统读取/proc/cpuinfo 文件中 CPU 的类型等多种信息

echo on
adb shell cat /proc/cpuinfo > Cpuinfo.txt

导出数据如下

processor   : 0
Processor   : AArch64 Processor rev 4 (aarch64)
model name  : AArch64 Processor rev 4 (aarch64)
BogoMIPS    : 26.00
Features    : fp asimd evtstrm aes pmull sha1 sha2 crc32
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part    : 0xd03
CPU revision    : 4

processor   : 1
Processor   : AArch64 Processor rev 4 (aarch64)
model name  : AArch64 Processor rev 4 (aarch64)
BogoMIPS    : 26.00
Features    : fp asimd evtstrm aes pmull sha1 sha2 crc32
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part    : 0xd03
CPU revision    : 4

processor   : 2
Processor   : AArch64 Processor rev 4 (aarch64)
model name  : AArch64 Processor rev 4 (aarch64)
BogoMIPS    : 26.00
Features    : fp asimd evtstrm aes pmull sha1 sha2 crc32
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part    : 0xd03
CPU revision    : 4

processor   : 3
Processor   : AArch64 Processor rev 4 (aarch64)
model name  : AArch64 Processor rev 4 (aarch64)
BogoMIPS    : 26.00
Features    : fp asimd evtstrm aes pmull sha1 sha2 crc32
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part    : 0xd03
CPU revision    : 4

Hardware    : MT6739WA

processor : 0 ~ processor : 3 表示 4 核 CPU

二、参数解释及可以获取的信息

1.参数解释

processor   : 0[系统中逻辑处理核的编号。对于单核处理器，则认为是其CPU编号，对于多核处理器则可以是物理核、或者使用超线程技术虚拟的逻辑核]
Processor   : AArch64 Processor rev 4 (aarch64)[CPU 架构， 64bit aarch64 表示 kernel]
model name  : AArch64 Processor rev 4 (aarch64)[CPU属于的名字及其编号、标称主频]
BogoMIPS    : 26.00 [在系统内核启动时粗略测算的CPU速度（Million Instructions Per Second）]
Features    : fp asimd evtstrm aes pmull sha1 sha2 crc32
CPU implementer : 0x41 [ARM 架构 cpu.h]
CPU architecture: 8
CPU variant : 0x0
CPU part    : 0xd03 [ARM_CPU_PART_CORTEX_A53 架构 cputype.h]
CPU revision    : 4 [4 配置版本或者配置修正]<1 第一批 2 修订版，改进版>

Hardware    : MT6739WA[品牌]

2.信息获取

1. 查看 kernel 的运行位数，是64或者32位数
2. 查看 CPU 的核数
3. 查看 CPU 的架构和名称

3.相关涉及源码定义

/external/v8/src/base/cpu.h
44  // arm implementer/part information
45  int implementer() const { return implementer_; }
46  static const int ARM = 0x41;
47  static const int NVIDIA = 0x4e;
48  static const int QUALCOMM = 0x51;

/kernel-3.18/arch/arm64/include/asm/cputype.h
8#define ARM_CPU_PART_AEM_V8    0xD0F
69#define ARM_CPU_PART_FOUNDATION   0xD00
70#define ARM_CPU_PART_CORTEX_A57   0xD07
71#define ARM_CPU_PART_CORTEX_A72   0xD08
72#define ARM_CPU_PART_CORTEX_A53   0xD03

三、参考源码

1./external/v8/src/base/cpu.h

// Copyright 2006-2013 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// This module contains the architecture-specific code. This make the rest of
6// the code less dependent on differences between different processor
7// architecture.
8// The classes have the same definition for all architectures. The
9// implementation for a particular architecture is put in cpu_<arch>.cc.
10// The build system then uses the implementation for the target architecture.
11//
12
13#ifndef V8_BASE_CPU_H_
14#define V8_BASE_CPU_H_
15
16#include "src/base/macros.h"
17
18namespace v8 {
19namespace base {
20
21// ----------------------------------------------------------------------------
22// CPU
23//
24// Query information about the processor.
25//
26// This class also has static methods for the architecture specific functions.
27// Add methods here to cope with differences between the supported
28// architectures. For each architecture the file cpu_<arch>.cc contains the
29// implementation of these static functions.
30
31class CPU FINAL {
32 public:
33  CPU();
34
35  // x86 CPUID information
36  const char* vendor() const { return vendor_; }
37  int stepping() const { return stepping_; }
38  int model() const { return model_; }
39  int ext_model() const { return ext_model_; }
40  int family() const { return family_; }
41  int ext_family() const { return ext_family_; }
42  int type() const { return type_; }
43
44  // arm implementer/part information
45  int implementer() const { return implementer_; }
46  static const int ARM = 0x41;
47  static const int NVIDIA = 0x4e;
48  static const int QUALCOMM = 0x51;
49  int architecture() const { return architecture_; }
50  int part() const { return part_; }
51  static const int ARM_CORTEX_A5 = 0xc05;
52  static const int ARM_CORTEX_A7 = 0xc07;
53  static const int ARM_CORTEX_A8 = 0xc08;
54  static const int ARM_CORTEX_A9 = 0xc09;
55  static const int ARM_CORTEX_A12 = 0xc0c;
56  static const int ARM_CORTEX_A15 = 0xc0f;
57
58  // General features
59  bool has_fpu() const { return has_fpu_; }
60
61  // x86 features
62  bool has_cmov() const { return has_cmov_; }
63  bool has_sahf() const { return has_sahf_; }
64  bool has_mmx() const { return has_mmx_; }
65  bool has_sse() const { return has_sse_; }
66  bool has_sse2() const { return has_sse2_; }
67  bool has_sse3() const { return has_sse3_; }
68  bool has_ssse3() const { return has_ssse3_; }
69  bool has_sse41() const { return has_sse41_; }
70  bool has_sse42() const { return has_sse42_; }
71
72  // arm features
73  bool has_idiva() const { return has_idiva_; }
74  bool has_neon() const { return has_neon_; }
75  bool has_thumb2() const { return has_thumb2_; }
76  bool has_vfp() const { return has_vfp_; }
77  bool has_vfp3() const { return has_vfp3_; }
78  bool has_vfp3_d32() const { return has_vfp3_d32_; }
79
80  // mips features
81  bool is_fp64_mode() const { return is_fp64_mode_; }
82
83 private:
84  char vendor_[13];
85  int stepping_;
86  int model_;
87  int ext_model_;
88  int family_;
89  int ext_family_;
90  int type_;
91  int implementer_;
92  int architecture_;
93  int part_;
94  bool has_fpu_;
95  bool has_cmov_;
96  bool has_sahf_;
97  bool has_mmx_;
98  bool has_sse_;
99  bool has_sse2_;
100  bool has_sse3_;
101  bool has_ssse3_;
102  bool has_sse41_;
103  bool has_sse42_;
104  bool has_idiva_;
105  bool has_neon_;
106  bool has_thumb2_;
107  bool has_vfp_;
108  bool has_vfp3_;
109  bool has_vfp3_d32_;
110  bool is_fp64_mode_;
111};
112
113} }  // namespace v8::base
114
115#endif  // V8_BASE_CPU_H_

2./kernel-3.18/arch/arm64/include/asm/cputype.h

1/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_CPUTYPE_H
17#define __ASM_CPUTYPE_H
18
19#define INVALID_HWID      ULONG_MAX
20
21#define MPIDR_UP_BITMASK  (0x1 << 30)
22#define MPIDR_MT_BITMASK  (0x1 << 24)
23#define MPIDR_HWID_BITMASK    0xff00ffffff
24
25#define MPIDR_LEVEL_BITS_SHIFT    3
26#define MPIDR_LEVEL_BITS  (1 << MPIDR_LEVEL_BITS_SHIFT)
27#define MPIDR_LEVEL_MASK  ((1 << MPIDR_LEVEL_BITS) - 1)
28
29#define MPIDR_LEVEL_SHIFT(level) \
30  (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
31
32#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
33  ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
34
35#define read_cpuid(reg) ({                        \
36  u64 __val;                          \
37  asm("mrs    %0, " #reg : "=r" (__val));         \
38  __val;                              \
39})
40
41#define MIDR_REVISION_MASK    0xf
42#define MIDR_REVISION(midr)   ((midr) & MIDR_REVISION_MASK)
43#define MIDR_PARTNUM_SHIFT    4
44#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
45#define MIDR_PARTNUM(midr)    \
46  (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
47#define MIDR_ARCHITECTURE_SHIFT   16
48#define MIDR_ARCHITECTURE_MASK    (0xf << MIDR_ARCHITECTURE_SHIFT)
49#define MIDR_ARCHITECTURE(midr)   \
50  (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
51#define MIDR_VARIANT_SHIFT    20
52#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
53#define MIDR_VARIANT(midr)    \
54  (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
55#define MIDR_IMPLEMENTOR_SHIFT    24
56#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
57#define MIDR_IMPLEMENTOR(midr)    \
58  (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
59
60#define MIDR_CPU_PART(imp, partnum) \
61  (((imp)         << MIDR_IMPLEMENTOR_SHIFT) | \
62  (0xf            << MIDR_ARCHITECTURE_SHIFT) | \
63  ((partnum)      << MIDR_PARTNUM_SHIFT))
64
65#define ARM_CPU_IMP_ARM       0x41
66#define ARM_CPU_IMP_APM       0x50
67
68#define ARM_CPU_PART_AEM_V8   0xD0F
69#define ARM_CPU_PART_FOUNDATION   0xD00
70#define ARM_CPU_PART_CORTEX_A57   0xD07
71#define ARM_CPU_PART_CORTEX_A72   0xD08
72#define ARM_CPU_PART_CORTEX_A53   0xD03
73
74#define APM_CPU_PART_POTENZA  0x000
75
76#define ID_AA64MMFR0_BIGENDEL0_SHIFT  16
77#define ID_AA64MMFR0_BIGENDEL0_MASK   (0xf << ID_AA64MMFR0_BIGENDEL0_SHIFT)
78#define ID_AA64MMFR0_BIGENDEL0(mmfr0) \
79  (((mmfr0) & ID_AA64MMFR0_BIGENDEL0_MASK) >> ID_AA64MMFR0_BIGENDEL0_SHIFT)
80#define ID_AA64MMFR0_BIGEND_SHIFT 8
81#define ID_AA64MMFR0_BIGEND_MASK  (0xf << ID_AA64MMFR0_BIGEND_SHIFT)
82#define ID_AA64MMFR0_BIGEND(mmfr0)    \
83  (((mmfr0) & ID_AA64MMFR0_BIGEND_MASK) >> ID_AA64MMFR0_BIGEND_SHIFT)
84
85#define SCTLR_EL1_CP15BEN (0x1 << 5)
86#define SCTLR_EL1_SED     (0x1 << 8)
87
88#ifndef __ASSEMBLY__
89
90/*
91 * The CPU ID never changes at run time, so we might as well tell the
92 * compiler that it's constant.  Use this function to read the CPU ID
93 * rather than directly reading processor_id or read_cpuid() directly.
94 */
95static inline u32 __attribute_const__ read_cpuid_id(void)
96{
97  return read_cpuid(MIDR_EL1);
98}
99
100static inline u64 __attribute_const__ read_cpuid_mpidr(void)
101{
102 return read_cpuid(MPIDR_EL1);
103}
104
105static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
106{
107 return MIDR_IMPLEMENTOR(read_cpuid_id());
108}
109
110static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
111{
112 return MIDR_PARTNUM(read_cpuid_id());
113}
114
115static inline u32 __attribute_const__ read_cpuid_cachetype(void)
116{
117 return read_cpuid(CTR_EL0);
118}
119
120static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
121{
122 return (ID_AA64MMFR0_BIGEND(mmfr0) == 0x1) ||
123     (ID_AA64MMFR0_BIGENDEL0(mmfr0) == 0x1);
124}
125#endif /* __ASSEMBLY__ */
126
127#endif