全志A10s芯片参数,处理器性能详细介绍

CPU

ARM Cortex-A8 Core

32KB I-Cache and 32KB D-Cache

256KB L2 Cache

NEON SIMD Coprocessor

Jazelle RCT Acceleration

GPU

3D Graphic Engine

 -Support Open GL ES 1.1/ 2.0 and open VG 1.1

VPU

 Video Decoding (FULL HD)

- Support multi-format video decoding, including VP8, AVS, H.264, H.263, VC-1, MPEG-1/2/4

    Video Encoding

- Support video encoding in H.264 MP format

- Up to1920*1080@30fps

Display Processing Ability

Four moveable and size-adjustable layers

Support multi-format image input

Support image enhancement processor

Support Alpha blending / anti-flicker

Support Hardware cursor

Support output color correction (luminance / hue / saturation etc)

Display Output Ability

Support HDMI V1.3

LCD interface (CPU / Sync RGB )

Support CVBS

Image Input Ability

Camera sensor interface

8 bits input data

Support CCIR656 protocol for NTSC and PAL

Memory

32-bit SDRAM controller

Support DDR2 SDRAM and DDR3 SDRAM up to 533MHz

Memory Capacity up to 16 G-bits

8-bit NAND Flash Controller with 4 CE and 2RB signals

Support SLC/MLC/TLC/DDR NAND

64-bit ECC

External Peripherals

One USB 2.0 DRD(Dual-Role Device) controller for general application and one USB EHCI/OHCI controller for host application

Three high-speed memory controllers supporting SD version 2.0 and eMMC version 4.3

Four UARTs:UART0 is 2-wires,UART1 is 8-wires,UART2 and UART3 are 4-wires

Three SPI controllers

Three Two-Wire Interface(TWI) Controllers

Key Matrix (8x8) with internal debounce filter

IR controller supporting CIR remoter

One embedded TS SPI/ SSI for DTV application

One 10/100Mbps Ethernet MAC

2-Ch 6-bit LRADC for line control

Internal 4-wire touch panel controller with pressure sensor and 2-point touch

System Peripherals

8-Ch normal DMA and 8-Ch dedicated DMA

Internal 48KB SRAM on chip

6 asynchronic timers, 2 synchronic timers, 1 watchdog, and 2 AVS counters

Security System

Support DES/3DES/AES encryption and decryption.

Support SHA-1, MD5 message digest

Support 160-bit hardware PRNG with 192-bit seed

128-bit EFUSE chip ID

Package

TFBGA336package