MR_2004 bringup

1.修改ram内存从2G 到4G，包括bootload 的修改，kernel修改，M4修改。

boot修改：

diff --git a/project/auto2712m-p1v1-2G-emmc.mk b/project/auto2712m-p1v1-2G-emmc.mk
index 998b358..b7d76db 100644
--- a/project/auto2712m-p1v1-2G-emmc.mk
+++ b/project/auto2712m-p1v1-2G-emmc.mk
@@ -6,11 +6,11 @@ WITH_KERNEL_VM := 1
 WITH_LINKER_GC := 1
 
 CA35_FREQ := CA35_FREQ_1196MHZ
-CA72_FREQ := CA72_FREQ_1196MHZ
+CA72_FREQ := CA72_FREQ_1599MHZ
 BOOTAPP := blxboot
 ENABLE_BUILTIN_BL33 := 0
-DRAM_SZ := DRAM_SZ_2G
-DRAM_BW := DRAM_BW_32BIT
+DRAM_SZ := DRAM_SZ_4G
+DRAM_BW := DRAM_BW_64BIT

kernel 修改：

diff --git a/arch/arm64/boot/dts/mediatek/auto2712m-p1v1-2G-emmc.dts b/arch/arm64/boot/dts/mediatek/auto2712m-p1v1-2G-emmc.dts
index 6fd8d99..62e51fd 100644
--- a/arch/arm64/boot/dts/mediatek/auto2712m-p1v1-2G-emmc.dts
+++ b/arch/arm64/boot/dts/mediatek/auto2712m-p1v1-2G-emmc.dts
@@ -82,3 +82,5 @@
         fsmgr_flags = "wait";
     };
 };
+
+#include "iauto-baltica-overlay.dtsi"
\ No newline at end of file
diff --git a/arch/arm64/boot/dts/mediatek/ultrafastrvc/ultrafastrvc_mipi.dts b/arch/arm64/boot/dts/mediatek/ultrafastrvc/ultrafastrvc_mipi.dts
index da08a60..2430756 100644
--- a/arch/arm64/boot/dts/mediatek/ultrafastrvc/ultrafastrvc_mipi.dts
+++ b/arch/arm64/boot/dts/mediatek/ultrafastrvc/ultrafastrvc_mipi.dts
@@ -42,6 +42,7 @@
              <&topckgen CLK_TOP_UART_SEL>,
              <&infracfg CLK_INFRA_GCE>,
              <&pericfg CLK_PERI_UART4>,
+             <&pericfg CLK_PERI_UART1>,
              <&mmsys CLK_MM_DISP_PWM0_26M>,
              <&mmsys CLK_MM_DISP_PWM0_MM>,
              <&mmsys CLK_MM_DISP_PWM1_26M>,

M4 修改：

diff --git a/drivers/CM4_A/mt2712/display/mtk_lvds.c b/drivers/CM4_A/mt2712/display/mtk_lvds.c
index 78f3a62..e49bfa2 100644
--- a/drivers/CM4_A/mt2712/display/mtk_lvds.c
+++ b/drivers/CM4_A/mt2712/display/mtk_lvds.c
@@ -181,6 +181,8 @@ static void mtk_lvds_tx_power_on_signal(struct display_mode_info *mode)
 
     if (mode->type == LCM_TYPE_DUAL_LVDS || mode->type == LCM_TYPE_SINGLE_LVDS_ON_TX0)
         writel(reg, LVDATX0 + LVDSTX_CTL4);
+    
+    writel(0x00c10fc8, LVDATX1 + LVDSTX_CTL2);
 }
 
 static void mtk_lvds_tx_power_off_signal(struct display_mode_info *mode)
@@ -242,6 +244,9 @@ int32_t mtk_lvds_enable(struct display_mode_info *mode)
           (~RG_DPMODE);
     writel(reg, LVDS_BASE + LVDS_CTRL02);
 
+    writel(0x3A243210, LVDS_BASE + LLV_DO_SEL);
+    writel(0x1A009000, LVDS_BASE + CKO_SEL);
+    writel(0x09E00000, LVDS_BASE + PN_SWAP);
     return 0;
 }
 
diff --git a/drivers/CM4_A/mt2712/panel/panel-simple.c b/drivers/CM4_A/mt2712/panel/panel-simple.c
index a691ebc..c6a2cb4 100644
--- a/drivers/CM4_A/mt2712/panel/panel-simple.c
+++ b/drivers/CM4_A/mt2712/panel/panel-simple.c
@@ -25,7 +25,14 @@ int32_t lcm_if_enable(struct display_mode_info *mode)
     /* to do
         config panel power and control pin
     */
-
+    gpio_set_mode(GPIO12, GPIO_MODE_GPIO);
+    gpio_set_dir(GPIO12, GPIO_DIR_OUT);
+    gpio_set_out(GPIO12, GPIO_OUT_ONE);
+    vTaskDelay(pdMS_TO_TICKS(20));
+
+    gpio_set_mode(GPIO9, GPIO_MODE_GPIO);
+    gpio_set_dir(GPIO9, GPIO_DIR_OUT);
+    gpio_set_out(GPIO9, GPIO_OUT_ONE);
     #endif
 
     if ((mode->type == LCM_TYPE_DUAL_LVDS)
@@ -69,19 +76,19 @@ int32_t lcm_if_disable(struct display_mode_info *mode)
 int32_t lcm_if_getmode(struct display_mode_info *mode)
 {
 #ifdef PANEL_AUO_G133HAN01
-    mode->type = LCM_TYPE_DUAL_LVDS;
-    mode->clock = 141200;
-    mode->hdisplay = 1920;
-    mode->hsync_start = 1920 + 108;
-    mode->hsync_end = 1920 + 108 + 20;
-    mode->htotal = 1920 + 108 + 20 + 60;
-    mode->vdisplay = 1080;
-    mode->vsync_start = 1080 + 16;
-    mode->vsync_end = 1080 + 16 + 10;
-    mode->vtotal = 1080 + 16 + 10 + 10;
+    mode->type = LCM_TYPE_SINGLE_LVDS_ON_TX1;
+    mode->clock = 66500;
+    mode->hdisplay = 1280;
+    mode->hsync_start = 1280 + 100;
+    mode->hsync_end = 1280 + 100 + 20;
+    mode->htotal = 1280 + 100 + 20 + 15;
+    mode->vdisplay = 720;
+    mode->vsync_start = 720 + 20;
+    mode->vsync_end = 720 + 20 + 20;
+    mode->vtotal = 720 + 20 + 20 + 23;
     mode->vrefresh = 60;
     mode->bpc = 8;
-    mode->bus_formats = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA;
+    mode->bus_formats = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG;
     mode->period_ns = 1000000;
 #endif
 
diff --git a/middleware/fastrvc/inc/fastrvc_setting.h b/middleware/fastrvc/inc/fastrvc_setting.h
index a574d82..e0e27de 100644
--- a/middleware/fastrvc/inc/fastrvc_setting.h
+++ b/middleware/fastrvc/inc/fastrvc_setting.h
@@ -80,8 +80,8 @@
 */
 #define DISPLAY_PIX_FMT            PIX_FMT_YUYV
 #define DISPLAY_OVL_FMT            PIX_DISP_YUYV
-#define DISPLAY_RESOLUTION_WIDTH    1920
-#define DISPLAY_RESOLUTION_HEIGHT    1080
+#define DISPLAY_RESOLUTION_WIDTH    1280
+#define DISPLAY_RESOLUTION_HEIGHT    720
 #define DISPLAY_IMAGE_SIZE        YUYV_IMAGE_SIZE(DISPLAY_RESOLUTION_WIDTH, DISPLAY_RESOLUTION_HEIGHT)
 
 #ifdef CFG_FASTLOGO_SUPPORT
diff --git a/project/CM4_A/mt2712/mt2712p1v1-4GB-MIPI/ProjectConfig.mk b/project/CM4_A/mt2712/mt2712p1v1-4GB-MIPI/ProjectConfig.mk
index 4aef1c6..cd79d84 100644
--- a/project/CM4_A/mt2712/mt2712p1v1-4GB-MIPI/ProjectConfig.mk
+++ b/project/CM4_A/mt2712/mt2712p1v1-4GB-MIPI/ProjectConfig.mk
@@ -34,7 +34,6 @@ CFG_VIDEO_CORE_SUPPORT = yes
 CFG_FASTLOGO_SUPPORT = yes
 CFG_FASTRVC_SUPPORT = yes
 CFG_OVL2_BRIDGE_SUPPORT = yes
-CFG_FASTRVC_APK_SUPPORT = yes
 CFG_FASTRVC_GUIDELINE_SUPPORT = yes
 CFG_DSP_IPC_SUPPORT = yes
 CFG_GPIO_SUPPORT = yes
@@ -49,3 +48,4 @@ CFG_MIPICSI_SUPPORT = yes
 CFG_MIPICSI0_SUPPORT = yes
 CFG_I2C_SUPPORT = yes
 CFG_BOOT_MODE_SUPPORT = yes
+CFG_UART_PORT1 = yes
\ No newline at end of file
diff --git a/project/CM4_A/mt2712/mt2712p1v1-non-4GB-MIPI/ProjectConfig.mk b/project/CM4_A/mt2712/mt2712p1v1-non-4GB-MIPI/ProjectConfig.mk
index ddca044..e4369fc 100644
--- a/project/CM4_A/mt2712/mt2712p1v1-non-4GB-MIPI/ProjectConfig.mk
+++ b/project/CM4_A/mt2712/mt2712p1v1-non-4GB-MIPI/ProjectConfig.mk
@@ -34,7 +34,6 @@ CFG_VIDEO_CORE_SUPPORT = yes
 CFG_FASTLOGO_SUPPORT = yes
 CFG_FASTRVC_SUPPORT = yes
 CFG_OVL2_BRIDGE_SUPPORT = yes
-CFG_FASTRVC_APK_SUPPORT = yes
 CFG_FASTRVC_GUIDELINE_SUPPORT = yes
 CFG_DSP_IPC_SUPPORT = yes
 CFG_GPIO_SUPPORT = yes
@@ -49,3 +48,4 @@ CFG_MIPICSI_SUPPORT = yes
 CFG_MIPICSI0_SUPPORT = yes
 CFG_I2C_SUPPORT = yes
 CFG_BOOT_MODE_SUPPORT = yes
+CFG_UART_PORT1 = yes
\ No newline at end of file
diff --git a/project/CM4_A/mt2712/platform/CMSIS/system.c b/project/CM4_A/mt2712/platform/CMSIS/system.c
index d2dc2c9..699ad38 100644
--- a/project/CM4_A/mt2712/platform/CMSIS/system.c
+++ b/project/CM4_A/mt2712/platform/CMSIS/system.c
@@ -23,4 +23,10 @@ void SystemInit(void)
      *
      */
     SCB->VTOR = ((uint32_t) 0x0);
+
+    /*
+    * Configure Systick clock source
+    */
+    reg = (SYST_NOREF | SYST_SKEW | SYST_TENMS);
+    writel(reg, CMSYS_SYST_CALIB);
 }
diff --git a/project/CM4_A/mt2712/platform/inc/FreeRTOSConfig.h b/project/CM4_A/mt2712/platform/inc/FreeRTOSConfig.h
index 86018b1..1a128aa 100644
--- a/project/CM4_A/mt2712/platform/inc/FreeRTOSConfig.h
+++ b/project/CM4_A/mt2712/platform/inc/FreeRTOSConfig.h
@@ -91,7 +91,8 @@ extern uint32_t SystemCoreClock;
 #define configUSE_TICKLESS_IDLE          0
 #endif
 #define configCPU_CLOCK_HZ               ( SystemCoreClock )
-#define configSYSTICK_CLOCK_HZ           (32000)
+//#define configSYSTICK_CLOCK_HZ           (32000)
+#define configSYSTICK_CLOCK_HZ ( SystemCoreClock )
 #define configTICK_RATE_HZ               ( ( TickType_t ) 1000 )
 #ifdef CFG_PD_SUPPORT
 #define configMAX_PRIORITIES             (8)
diff --git a/project/CM4_A/mt2712/platform/inc/scp_regs.h b/project/CM4_A/mt2712/platform/inc/scp_regs.h
index a5f4c4c..cf620b3 100644
--- a/project/CM4_A/mt2712/platform/inc/scp_regs.h
+++ b/project/CM4_A/mt2712/platform/inc/scp_regs.h
@@ -49,6 +49,11 @@
 #define SEMAPHORE0                  0x38
 #define SEMAPHORE1                  0x3C
 
+#define CMSYS_SYST_CALIB        (SCP_MODULE_BASE + 0x40)
+#define SYST_NOREF                BIT(25)
+#define SYST_SKEW                BIT(24)
+#define SYST_TENMS                (SystemCoreClock / 100)
+
 #define CMSYS_CONFIG_REG        (SCP_MODULE_BASE + 0x44)
     #define ENABLE_FPU        (0x1 << 1)
 
device 编译修改：

diff --git a/BoardConfig.mk b/BoardConfig.mk
index 18b1bce..833ae72 100644
--- a/BoardConfig.mk
+++ b/BoardConfig.mk
@@ -154,6 +154,7 @@ MTK_TINYSYS_TARGET_PROJECT := mt2712p1v1-non-4GB-MIPI
 else
 MTK_TINYSYS_TARGET_PROJECT := mt2712p1v1-4GB-MIPI
 endif
+MTK_TINYSYS_TARGET_PROJECT := mt2712p1v1-4GB-MIPI
 DISABLE_MTK_CONFIG_CHECK := yes
 KCONFIG_DELTA += ultrafastrvc/ultrafastrvc_mipi
 endif
 

 

diff --git a/car_mt2712_vp3/car_mt2712_vp3.mk b/car_mt2712_vp3/car_mt2712_vp3.mk
index 122e4b9..14a3caf 100644
--- a/car_mt2712_vp3/car_mt2712_vp3.mk
+++ b/car_mt2712_vp3/car_mt2712_vp3.mk
@@ -9,7 +9,8 @@ PRODUCT_MODEL := Car on mt2712
 # LINUX_KERNEL_VERSION should be the same with android kernel directory
 # eg kernel-3.18 for kernel-4.4.
 LINUX_KERNEL_VERSION = kernel-4.9
-KERNEL_DEFCONFIG := mt2712_android_defconfig
+#KERNEL_DEFCONFIG := mt2712_android_defconfig
+KERNEL_DEFCONFIG := mt2712_dxxxx_newhard_android_defconfig
 ifneq ($(TARGET_BUILD_VARIANT), user)
 KERNEL_DEBUG_DELTA := mt2712_android_debug
 endif