E203 蜂鸟 RISC-V处理器代码阅读笔记 之 通用触发器模块定义 sirv_gnrl_dffs.v

这个文章记录了我学习RISC-V蜂鸟E203处理器的学习历程
针对代码的学习，我结合自己的理解对每个module的接口，以及内部关键信号做了详细的注释说明
原创不易，请保护版权，转载联系作者，并请注明出处，标出原始链接,谢谢~~~
sirv_gnrl_dffs.v

 /*                                                                      
 Copyright 2017 Silicon Integrated Microelectronics, Inc.                
                                                                         
 Licensed under the Apache License, Version 2.0 (the "License");         
 you may not use this file except in compliance with the License.        
 You may obtain a copy of the License at                                 
                                                                         
     http://www.apache.org/licenses/LICENSE-2.0                          
                                                                         
  Unless required by applicable law or agreed to in writing, software    
 distributed under the License is distributed on an "AS IS" BASIS,       
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and     
 limitations under the License.                                          
 */                                                                      
                                                                         
                                                                         
                                                                         
//=====================================================================
//--        _______   ___
//--       (   ____/ /__/
//--        \ \     __
//--     ____\ \   / /
//--    /_______\ /_/   MICROELECTRONICS
//--
//=====================================================================
//
// Designer   : Bob Hu
//
// Description:
//  All of the general DFF and Latch modules
//
// ====================================================================

//


//
// ===========================================================================
//
// Description:
//  Verilog module sirv_gnrl DFF with Load-enable and Reset
//  Default reset value is 1
//
// ===========================================================================

module sirv_gnrl_dfflrs # ( // 带有使能和异步复位功能的D触发器，最后的s表示上电默认状态是1
  parameter DW = 32
) (

  input               lden, //使能信号，只有非复位状态下，该信号有效，寄存器的输出才会更新成dnxt的值
  input      [DW-1:0] dnxt,
  output     [DW-1:0] qout,

  input               clk