sunxi-fel适配原理和新芯片烧录功能的适配

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移植补丁

diff --git a/.gitignore b/.gitignore
index 1db11da..7618ae1 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,3 +8,7 @@ sunxi-pio
 version.h
 *.o
 *.swp
+cscope.*
+tags
+.err
+*.fex
diff --git a/aw_spi.h b/aw_spi.h
new file mode 100644
index 0000000..5866523
--- /dev/null
+++ b/aw_spi.h
@@ -0,0 +1,868 @@
+#ifndef __AW_SPI_H__
+#define __AW_SPI_H__
+
+#include <stdint.h>
+
+//typedef unsigned int uint32_t;
+//typedef unsigned short uint16_t;
+//typedef unsigned char uint8_t;
+#ifdef __cplusplus
+extern "C" {
+#endif
+/********************** private ************************************/
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+typedef struct
+{
+    volatile uint32_t RESERVED0;         /* Reserved, 0x00                                        Address offset: 0x00   */
+    volatile uint32_t GCR;               /* SPI Global Control Register,                          Address offset: 0x04   */
+    volatile uint32_t TCR;               /* SPI Transfer Control Register,                        Address offset: 0x08   */
+    volatile uint32_t RESERVED1[1];      /* Reserved, 0x0C                                                               */
+    volatile uint32_t IER;               /* SPI Interrupt Control Register,                       Address offset: 0x10   */
+    volatile uint32_t ISR;               /* SPI Interrupt Status Register,                        Address offset: 0x14   */
+    volatile uint32_t FCR;               /* SPI FIFO Control Register,                            Address offset: 0x18   */
+    volatile uint32_t FSR;               /* SPI FIFO Status Register,                             Address offset: 0x1C   */
+    volatile uint32_t WCR;               /* SPI Wait Clock Counter Register,                      Address offset: 0x20   */
+    volatile uint32_t CCR;               /* SPI Clock Rate Control Register,                      Address offset: 0x24   */
+    
+    volatile uint32_t RESERVED2[2];      /* Reserved, 0x28-0x2C                                                          */
+    volatile uint32_t MBC;               /* SPI Master mode Burst Control Register,               Address offset: 0x30   */
+    volatile uint32_t MTC;               /* SPI Master mode Transmit Counter Register,            Address offset: 0x34   */
+    volatile uint32_t BCC;               /* SPI Burst Control Register,                           Address offset: 0x38   */
+    volatile uint32_t RESERVED4[113];    /* Reserved, 0x3C-0x1FC                                                         */
+    volatile uint32_t TXD;               /* SPI TX Date Register,                                 Address offset: 0x200  */
+    volatile uint32_t RESERVED5[63];     /* Reserved, 0x204-0x2FC                                                        */
+    volatile uint32_t RXD;               /* SPI RX Date Register,                                 Address offset: 0x300  */
+} SPI_T;
+
+/*
+ * @brief SPI Global Control Register
+ */
+#define SPI_CTRL_RST_SHIFT                  (31)
+#define SPI_CTRL_RST_MASK                   (0x1U << SPI_CTRL_RST_SHIFT)
+
+#define SPI_CTRL_TP_EN_SHIFT                (7)
+#define SPI_CTRL_TP_EN_MASK                 (0x1U << SPI_CTRL_TP_EN_SHIFT)
+
+#define SPI_CTRL_MODE_SHIFT                 (1)
+#define SPI_CTRL_MODE_MASK                  (0x1U << SPI_CTRL_MODE_SHIFT)
+typedef enum
+{
+    SPI_CTRL_MODE_SLAVE = 0 << SPI_CTRL_MODE_SHIFT,
+    SPI_CTRL_MODE_MASTER = 1 << SPI_CTRL_MODE_SHIFT
+} SPI_CTRL_Mode;
+
+#define SPI_CTRL_EN_SHIFT                   (0)
+#define SPI_CTRL_EN_MASK                    (0x1U << SPI_CTRL_EN_SHIFT)
+typedef enum
+{
+    SPI_CTRL_EN_DISABLE = 0 << SPI_CTRL_EN_SHIFT,
+    SPI_CTRL_EN_ENABLE = 1 << SPI_CTRL_EN_SHIFT
+} SPI_CTRL_En;
+
+/*
+ * @brief SPI Transfer Control Register
+ */
+#define SPI_TCTRL_XCH_SHIFT                 (31)
+#define SPI_TCTRL_XCH_MASK                  (0x1U << SPI_TCTRL_XCH_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_XCH_IDLE = 0 << SPI_TCTRL_XCH_SHIFT,
+    SPI_TCTRL_XCH_START = 1 << SPI_TCTRL_XCH_SHIFT
+} SPI_TCTRL_Xch;
+
+#define SPI_TCTRL_SDM_SHIFT                 (13)
+#define SPI_TCTRL_SDM_MASK                  (0x1U << SPI_TCTRL_SDM_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_SDM_SAMPLE_NODELAY = 1 << SPI_TCTRL_SDM_SHIFT,
+    SPI_TCTRL_SDM_SAMPLE_DELAY = 0 << SPI_TCTRL_SDM_SHIFT
+} SPI_TCTRL_Sdm;
+
+#define SPI_TCTRL_FBS_SHIFT                 (12)
+#define SPI_TCTRL_FBS_MASK                  (0x1U << SPI_TCTRL_FBS_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_FBS_MSB = 0 << SPI_TCTRL_FBS_SHIFT,
+    SPI_TCTRL_FBS_LSB = 1 << SPI_TCTRL_FBS_SHIFT
+} SPI_TCTRL_Fbs;
+
+#define SPI_TCTRL_SDC_SHIFT                 (11)
+#define SPI_TCTRL_SDC_MASK                  (0x1U << SPI_TCTRL_SDC_SHIFT)
+
+#define SPI_TCTRL_RPSM_SHIFT                (10)
+#define SPI_TCTRL_RPSM_MASK                 (0x1U << SPI_TCTRL_RPSM_SHIFT)
+
+#define SPI_TCTRL_DDB_SHIFT                 (9)
+#define SPI_TCTRL_DDB_MASK                  (0x1U << SPI_TCTRL_DDB_SHIFT)
+
+#define SPI_TCTRL_DHB_SHIFT                 (8)
+#define SPI_TCTRL_DHB_MASK                  (0x1U << SPI_TCTRL_DHB_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_DHB_FULL_DUPLEX = 0 << SPI_TCTRL_DHB_SHIFT,
+    SPI_TCTRL_DHB_HALF_DUPLEX = 1 << SPI_TCTRL_DHB_SHIFT
+} SPI_TCTRL_DHB_Duplex;
+
+#define SPI_TCTRL_SS_LEVEL_SHIFT            (7)
+#define SPI_TCTRL_SS_LEVEL_MASK             (0x1U << SPI_TCTRL_SS_LEVEL_SHIFT)
+
+#define SPI_TCTRL_SS_OWNER_SHIFT            (6)
+#define SPI_TCTRL_SS_OWNER_MASK             (0x1U << SPI_TCTRL_SS_OWNER_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_SS_OWNER_CONTROLLER = 0 << SPI_TCTRL_SS_OWNER_SHIFT,
+    SPI_TCTRL_SS_OWNER_SOFTWARE = 1 << SPI_TCTRL_SS_OWNER_SHIFT
+} SPI_TCTRL_SS_OWNER;
+
+#define SPI_TCTRL_SS_SEL_SHIFT              (4)
+#define SPI_TCTRL_SS_SEL_MASK               (0x3U << SPI_TCTRL_SS_SEL_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_SS_SEL_SS0 = 0 << SPI_TCTRL_SS_SEL_SHIFT,
+    SPI_TCTRL_SS_SEL_SS1 = 1 << SPI_TCTRL_SS_SEL_SHIFT,
+    SPI_TCTRL_SS_SEL_SS2 = 2 << SPI_TCTRL_SS_SEL_SHIFT,
+    SPI_TCTRL_SS_SEL_SS3 = 3 << SPI_TCTRL_SS_SEL_SHIFT
+} SPI_TCTRL_SS_Sel;
+
+#define SPI_TCTRL_SS_CTL_SHIFT              (3)
+#define SPI_TCTRL_SS_CTL_MASK               (0x1U << SPI_TCTRL_SS_CTL_SHIFT)
+
+#define SPI_TCTRL_SPOL_SHIFT                (2)
+#define SPI_TCTRL_SPOL_MASK                 (0x1U << SPI_TCTRL_SPOL_SHIFT)
+
+#define SPI_TCTRL_CPOL_SHIFT                (1)
+#define SPI_TCTRL_CPOL_MASK                 (0x1U << SPI_TCTRL_CPOL_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_CPOL_HIGH = 0 << SPI_TCTRL_CPOL_SHIFT,
+    SPI_TCTRL_CPOL_LOW = 1 << SPI_TCTRL_CPOL_SHIFT
+} SPI_TCTRL_Cpol;
+
+#define SPI_TCTRL_CPHA_SHIFT                (0)
+#define SPI_TCTRL_CPHA_MASK                 (0x1U << SPI_TCTRL_CPHA_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_CPHA_PHASE0  = 0 << SPI_TCTRL_CPHA_SHIFT,
+    SPI_TCTRL_CPHA_PHASE1  = 1 << SPI_TCTRL_CPHA_SHIFT
+} SPI_TCTRL_Cpha;
+
+typedef enum
+{
+    SPI_SCLK_Mode0 = 0 << SPI_TCTRL_CPHA_SHIFT,
+    SPI_SCLK_Mode1 = 1 << SPI_TCTRL_CPHA_SHIFT,
+    SPI_SCLK_Mode2 = 2 << SPI_TCTRL_CPHA_SHIFT,
+    SPI_SCLK_Mode3 = 3 << SPI_TCTRL_CPHA_SHIFT
+} SPI_SCLK_Mode;
+
+/*
+ * @brief SPI Interrupt Control Register
+ */
+#define SPI_IER_SS_INT_EN_SHIFT             (13)
+#define SPI_IER_SS_INT_EN_MASK              (0x1U << SPI_IER_SS_INT_EN_SHIFT)
+
+#define SPI_IER_TC_INT_EN_SHIFT             (12)
+#define SPI_IER_TC_INT_EN_MASK              (0x1U << SPI_IER_TC_INT_EN_SHIFT)
+
+#define SPI_IER_TF_UDR_INT_EN_SHIFT         (11)
+#define SPI_IER_TF_UDR_INT_EN_MASK          (0x1U << SPI_IER_TF_UDR_INT_EN_SHIFT)
+
+#define SPI_IER_TF_OVF_INT_EN_SHIFT         (10)
+#define SPI_IER_TF_OVF_INT_EN_MASK          (0x1U << SPI_IER_TF_OVF_INT_EN_SHIFT)
+
+#define SPI_IER_RF_UDR_INT_EN_SHIFT         (9)
+#define SPI_IER_RF_UDR_INT_EN_MASK          (0x1U << SPI_IER_RF_UDR_INT_EN_SHIFT)
+
+#define SPI_IER_RF_OVF_INT_EN_SHIFT         (8)
+#define SPI_IER_RF_OVF_INT_EN_MASK          (0x1U << SPI_IER_RF_OVF_INT_EN_SHIFT)
+
+#define SPI_IER_TF_FUL_INT_EN_SHIFT         (6)
+#define SPI_IER_TF_FUL_INT_EN_MASK          (0x1U << SPI_IER_TF_FUL_INT_EN_SHIFT)
+
+#define SPI_IER_TX_EMP_INT_EN_SHIFT         (5)
+#define SPI_IER_TX_EMP_INT_EN_MASK          (0x1U << SPI_IER_TX_EMP_INT_EN_SHIFT)
+
+#define SPI_IER_TX_ERQ_INT_EN_SHIFT         (4)
+#define SPI_IER_TX_ERQ_INT_EN_MASK          (0x1U << SPI_IER_TX_ERQ_INT_EN_SHIFT)
+
+#define SPI_IER_RF_FUL_INT_EN_SHIFT         (2)
+#define SPI_IER_RF_FUL_INT_EN_MASK          (0x1U << SPI_IER_RF_FUL_INT_EN_SHIFT)
+
+#define SPI_IER_RX_EMP_INT_EN_SHIFT         (1)
+#define SPI_IER_RX_EMP_INT_EN_MASK          (0x1U << SPI_IER_RX_EMP_INT_EN_SHIFT)
+
+#define SPI_IER_RF_RDY_INT_EN_SHIFT         (0)
+#define SPI_IER_RF_RDY_INT_EN_MASK          (0x1U << SPI_IER_RF_RDY_INT_EN_SHIFT)
+
+/*
+ * @brief SPI Interrupt Status Register
+ */
+#define SPI_STA_SSI_SHIFT                   (13)
+#define SPI_STA_SSI_MASK                    (0x1U << SPI_STA_SSI_SHIFT)
+
+#define SPI_STA_TC_SHIFT                    (12)
+#define SPI_STA_TC_MASK                     (0x1U << SPI_STA_TC_SHIFT)
+
+#define SPI_STA_TF_UDF_SHIFT                (11)
+#define SPI_STA_TF_UDF_MASK                 (0x1U << SPI_STA_TF_UDF_SHIFT)
+
+#define SPI_STA_TF_OVF_SHIFT                (10)
+#define SPI_STA_TF_OVF_MASK                 (0x1U << SPI_STA_TF_OVF_SHIFT)
+
+#define SPI_STA_RX_UDF_SHIFT                (9)
+#define SPI_STA_RX_UDF_MASK                 (0x1U << SPI_STA_RX_UDF_SHIFT)
+
+#define SPI_STA_RX_OVF_SHIFT                (8)
+#define SPI_STA_RX_OVF_MASK                 (0x1U << SPI_STA_RX_OVF_SHIFT)
+
+#define SPI_STA_TX_FULL_SHIFT               (6)
+#define SPI_STA_TX_FULL_MASK                (0x1U << SPI_STA_TX_FULL_SHIFT)
+
+#define SPI_STA_TX_EMP_SHIFT                (5)
+#define SPI_STA_TX_EMP_MASK                 (0x1U << SPI_STA_TX_EMP_SHIFT)
+
+#define SPI_STA_TX_READY_SHIFT              (4)
+#define SPI_STA_TX_READY_MASK               (0x1U << SPI_STA_TX_READY_SHIFT)
+
+#define SPI_STA_RX_FULL_SHIFT               (2)
+#define SPI_STA_RX_FULL_MASK                (0x1U << SPI_STA_RX_FULL_SHIFT)
+
+#define SPI_STA_RX_EMP_SHIFT                (1)
+#define SPI_STA_RX_EMP_MASK                 (0x1U << SPI_STA_RX_EMP_SHIFT)
+
+#define SPI_STA_RX_RDY_SHIFT                (0)
+#define SPI_STA_RX_RDY_MASK                 (0x1U << SPI_STA_RX_RDY_SHIFT)
+
+/*
+ * @brief SPI FIFO Control Register
+ */
+#define SPI_FCTL_TF_RST_SHIFT               (31)
+#define SPI_FCTL_TF_RST_MASK                (0x1U << SPI_FCTL_TF_RST_SHIFT)
+
+#define SPI_FCTL_TF_TEST_EN_SHIFT           (30)
+#define SPI_FCTL_TF_TEST_EN_MASK            (0x1U << SPI_FCTL_TF_TEST_EN_SHIFT)
+
+#define SPI_FCTL_TF_DRQ_EN_SHIFT            (24)
+#define SPI_FCTL_TF_DRQ_EN_MASK             (0x1U << SPI_FCTL_TF_DRQ_EN_SHIFT)
+#define SPI_FCTL_TF_DRQ_EN_BIT              HAL_BIT(24)
+
+#define SPI_FCTL_TX_TRIG_LEVEL_SHIFT        (16)
+#define SPI_FCTL_TX_TRIG_LEVEL_MASK         (0xFFU << SPI_FCTL_TX_TRIG_LEVEL_SHIFT)
+
+#define SPI_FCTL_RF_RST_SHIFT               (15)
+#define SPI_FCTL_RF_RST_MASK                (0x1U << SPI_FCTL_RF_RST_SHIFT)
+
+#define SPI_FCTL_RF_TEST_SHIFT              (14)
+#define SPI_FCTL_RF_TEST_MASK               (0x1U << SPI_FCTL_RF_TEST_SHIFT)
+
+#define SPI_FCTL_RF_DRQ_EN_SHIFT            (8)
+#define SPI_FCTL_RF_DRQ_EN_MASK             (0x1U << SPI_FCTL_RF_DRQ_EN_SHIFT)
+
+#define SPI_FCTL_RX_TRIG_LEVEL_SHIFT        (0)
+#define SPI_FCTL_RX_TRIG_LEVEL_MASK         (0xFFU << SPI_FCTL_RX_TRIG_LEVEL_SHIFT)
+
+/*
+ * @brief SPI FIFO Status Registe
+ */
+#define SPI_FST_TB_WR_SHIFT                 (31)
+#define SPI_FST_TB_WR_MASK                  (0x1U << SPI_FST_TB_WR_SHIFT)
+
+#define SPI_FST_TB_CNT_SHIFT                (28)
+#define SPI_FST_TB_CNT_MASK                 (0x7U << SPI_FST_TB_CNT_SHIFT)
+
+#define SPI_FST_TF_CNT_SHIFT                (16)
+#define SPI_FST_TF_CNT_MASK                 (0xFFU << SPI_FST_TF_CNT_SHIFT)
+
+#define SPI_FST_RB_WR_SHIFT                 (15)
+#define SPI_FST_RB_WR_MASK                  (0x1U << SPI_FST_RB_WR_SHIFT)
+
+#define SPI_FST_RB_CNT_SHIFT                (12)
+#define SPI_FST_RB_CNT_MASK                 (0x7U << SPI_FST_RB_CNT_SHIFT)
+
+#define SPI_FST_RF_CNT_SHIFT                (0)
+#define SPI_FST_RF_CNT_MASK                 (0xFFU << SPI_FST_RF_CNT_SHIFT)
+
+/*
+ * @brief SPI Wait Clock Counter Register
+ */
+#define SPI_WAIT_SWC_SHIFT                  (16)
+#define SPI_WAIT_SWC_MASK                   (0xFU << SPI_WAIT_SWC_SHIFT)
+
+#define SPI_WAIT_WCC_SHIFT                  (0)
+#define SPI_WAIT_WCC_MASK                   (0xFFFFU << SPI_WAIT_WCC_SHIFT)
+
+/*
+ * @brief SPI Clock Rate Control Register
+ */
+#define SPI_CCTR_DRS_SHIFT                  (12)
+#define SPI_CCTR_DRS_MASK                   (0x1U << SPI_CCTR_DRS_SHIFT)
+typedef enum
+{
+    SPI_CCTR_DRS_type_divRate1 = 0 << SPI_CCTR_DRS_SHIFT,
+    SPI_CCTR_DRS_type_divRate2 = 1 << SPI_CCTR_DRS_SHIFT
+} SPI_CCTR_DRS_type;
+
+#define SPI_CCTR_CDR1_SHIFT                 (8)
+#define SPI_CCTR_CDR1_MASK                  (0xFU << SPI_CCTR_CDR1_SHIFT)
+
+#define SPI_CCTR_CDR2_SHIFT                 (0)
+#define SPI_CCTR_CDR2_MASK                  (0xFFU << SPI_CCTR_CDR2_SHIFT)
+
+/*
+ * @brief SPI Master mode Burst Control Register
+ */
+#define SPI_BC_MBC_SHIFT                    (0)
+#define SPI_BC_MBC_MASK                     (0xFFFFFFU << SPI_BC_MBC_SHIFT)
+
+/*
+ * @brief SPI Master mode Transmit Counter Register
+ */
+#define SPI_TC_MWTC_SHIFT                   (0)
+#define SPI_TC_MWTC_MASK                    (0xFFFFFFU << SPI_TC_MWTC_SHIFT)
+
+/*
+ * @brief SPI Burst Control Register
+ */
+#define SPI_BCC_DRM_SHIFT                   (28)
+#define SPI_BCC_DRM_MASK                    (0x1U << SPI_BCC_DRM_SHIFT)
+
+#define SPI_BCC_DBC_SHIFT                   (24)
+#define SPI_BCC_DBC_MASK                    (0xFU