FPGA 按键控制数码管

module Digital(clk,key,dig,out);
	input clk,key;
	output dig;
	output[7:0] out;
	
	wire dig;
	reg[7:0] out;
	reg[4:0] count;
	
	assign dig=0;
	
	div(clk,clk_10hz);
	
	always@(posedge clk_10hz)
		begin		
			case( count )
				4'h0 : out = 8'hc0; //显示"0"
				4'h1 : out = 8'hf9; //显示"1"
				4'h2 : out = 8'ha4; //显示"2"
				4'h3 : out = 8'hb0; //显示"3"
				4'h4 : out = 8'h99; //显示"4"
				4'h5 : out = 8'h92; //显示"5"
				4'h6 : out = 8'h82; //显示"6"
				4'h7 : out = 8'hf8; //显示"7"
				4'h8 : out = 8'h80; //显示"8"
				4'h9 : out = 8'h90; //显示"9"
				4'ha : out = 8'h88; //显示"a"
				4'hb : out = 8'h83; //显示"b"
				4'hc : out = 8'hc6; //显示"c"
				4'hd : out = 8'ha1; //显示"d"
				4'he : out = 8'h86; //显示"e"
				4'hf : out = 8'h8e; //显示"f"
			endcase
			
			if( key==0 )
				count<=count+1;
			if( count>14 )
				count<=0;
		end
		
endmodule 

module div(clk,clk_10hz);
	input clk;
	output clk_10hz;
	
	reg[25:0] cnt;
	reg clk_10hz;
	
	always@(posedge clk)
		begin
			cnt<=cnt+1;
			if( cnt>2500000 )
				clk_10hz<=0;
			else if( cnt<2500000 )
				clk_10hz<=1;
			
			if( cnt>5000000 )
					cnt<=0;
		end
endmodule