hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Q2b: Another FSM

有报错， 没看出来错在哪

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    parameter A=     9'd1;
    parameter X0=     9'd2;
    parameter X1=     9'd3;
    parameter X2=     9'd4;
    parameter Y0=     9'd5;
    parameter Y1=      9'd6;
    parameter Y2=     9'd7;
    parameter YOK =  9'd8;
    parameter YERR = 9'd9;
    
    reg [8:0] state, next;
    
    //ff
    always @(posedge clk) begin
        if(!resetn)
            state = A;
        else
            state = next;
    end
    
    //trans
    always @(*) begin
        if(!resetn)
            next = A;
        else begin
            //next = X0;
            case (state)
                A: 
                    next = X0;
                X0: begin
                    if(x==1)
                        next = X1;
                    else
                        next = X0;
                end
                X1: begin
                    if(x==0)
                        next = X2;
                    else
                        next = X1;
                end
                X2: begin
                    if(x==1)
                        next = Y0;
                    else
                        next = X0;
                end
                Y0:begin
                    if(y==1)
                        next = YOK;
                    else 
                        next = Y1;
                end
                Y1:begin
                    if(y==1)
                        next = YOK;
                    else
                        next = YERR;
                end
                YOK:
                    next = YOK;
                YERR:
                    next = YERR;
                default:
                    next = A;
            endcase
        end     
    end
    
    //out
    always @(posedge clk) begin
        if ((state == A) && (next == X0) )
            f = 1;
        else
            f = 0;
    end
    
    always @(*) begin
    //always @(posedge clk) begin
        if ((state == Y0)||(state == Y1))
            g = 1;
        else if (state == YOK )
            g = 1;
        else 
            g = 0;
    end
    
endmodule