module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q);
always @ (posedge clk) begin
if(shift_ena)
q = {q[2:0], data};
if(count_ena)
q = q - 4'd1;
end
endmodule
hdlbits.01xz.net /Circuits/Building Larger Circuits/4-bit shift register and down counter
最新推荐文章于 2024-06-06 10:43:34 发布