1. AHB-RAM
1.1 ahb-ram 验证中,用到的 ahb_if 协议信号列表
提示:通常,根据信号列表,确定 ahb_if 有哪些数据类型
DUT ahb-ram 不支持 burst 传输。用到的是 比较简单的 部分 AHB 协议。
定义的这些 master_if 与 ahb-ram dut 连接。
有些信号虽然定义了,但是,暂时不会用(为了未来扩展使用)。
信号 | ahbram 中 apb_if (参考 vip 的 ahb_master_if 定义) | 对应 AHBRAM 模块的哪个信号 | 说明 |
---|---|---|---|
hclk | logic hclk | HCLK | |
hresetn | logic hresetn | HRESETn | |
master 信号,master -> bus | |||
haddr | logic[31:0] haddr | HADDR | AHB Addr Bus. addr bus for each master in the system. |
hburst | logic[2:0] hburst | 无 | 表明 transfer 是否为 burst 传输(的一部分) |
hbusreq | logic hbusreq | 无 | asserted by master to request access to the bus. |
hlock | logic hlock | 无 | asserted by master to carry out a locked trans. |
hsize | logic[2:0] hsize | HSIZE | indicates siae of transfer. (size : ) |
htrans | logic[1:0] htrans | HTRANS | indicates the type of transfer beding performed. ( type : ) |
hwdata | logic[31:0] hwdata | HWDATA | write data |
hwrite | logic hwrite | HWRITE | write signal. 1/0 : write/read. |
hprot | logic[3:0] hprot | 无 | protection control signals. (?) |
arbiter 信号 | |||
hgrant | logic hgrant | 无 | asserted by arbiter, indicate the requensting master has own the ownership of the bus. |
slave 信号, slave -> bus | |||
hready | logic hready | HREADYOUT | slave => bus ready response from selected slave. This signal is passed to all masters and slaves. |
hresp[1:0] | logic [1:0] hresp | HRESP | slave => bus, response signal, be passed to all AHB masters. |
hrdata[31:0] | logic[31:0] hrdata | HRDATA | read data |
AHBRAM 模块中,不知道如何连接的接口 (TO-DO) | |||
HSELBRAM | AHB periphreal select | ||
HREADY | AHB ready input |
1.2 AHB-RAM DUT 模块端口信号列表
AHB-RAM 模块端口信号 (as slave) | in/out | Transaction 中变量 | 说明 |
---|---|---|---|
HCLK | input | system bus clk | |
HRESETn | input | system bus reset | |
master -> slave | |||
HSELBRAM | input | 不需要 (default = 1) | AHB peripheral select |
HREADY | input | 无? | AHB ready input |
HTRANS[1:0] | input | trans_type_enum trans_type | AHB transfer type |
HSIZE[1:0] | input | 无? | AHB hsize |
HWRITE | input | xact_type | AHB hwrite |
HADDR[ADDR_WIDTH-1:0] | input | addr | AHB addr bus |
HWDATA[31:0] | input | data[ ] | write data bus |
slave -> master | |||
HREADYOUT | output | AHB ready output to S->M mux | |
HRESP | output | response_type_enum response_type | AHB response |
HRDATA | output | data[ ] | AHB read data bus |
1.3 Transaction
提示:参考 AMB_SPEC 中 ahb 协议信号、时序波形
说明:定义的很多数据类型,在本次测试不一定会使用;为了未来便于拓展
枚举类型定义:
提示:与 AMBA_SPEC 中信号对应
typedef enum | AHB SPEC signal | type name | 值定义 | note |
---|---|---|---|---|
respose Type | HRESP[1:0] (transfer response, AHB2) | response_type_enum | OKAY:00, ERROR:01, RETRY:10, SPLIT:11 | |
trans Type | HTRANS[2:0] | trans_type_enum | 00, 01, 10, 11 | |
burst_size | HSIZE[2:0] | burst_size_enum | 8/16/32/64/128/256/512/1024-bit () | (AHB RAM 不会用,因为不支持 burst) |
burst_type | ??? | |||
xact_type | HWRITE | READ:00 WRITE:01 IDLE_XACT:10 | ||
status_enum | ??? | INITIAL , PARTIAL_ACCEPT , ACCEPT , ABORTED |
Transaction 定义:
类的成员 | 对应的 DUT 接口信号 | 修饰 | note |
---|---|---|---|
wdata or rdata from bus | |||
bit[DATA_WIDTH -1:0] data[ ] | HWDATA , HRDATA | rand | |
bit[ADDR_WIDTH-1:0] addr | HADDR | rand | |
the burst size of a transaction | |||
burst_size_enum burst_size | 无(AHBRAM 不支持 Burst ) | rand | |
the burst type of a transaction | |||
burst_type_enum burst_type | 无(AHBRAM 不支持 Burst ) | rand | |
response from the slave | |||
response_type_enum response_type | HRESP | rand | |
response_type_enum all_beat_response[] | ?? | ||
int current_data_beat_num | ?? | the beat number of current transfer | |
status_enum status | ?? | status = INITIAL; | |
the type of current transfer (可能不会使用) | |||
trans_type_enum trans_type | HTRANS[1:0] | rand | |
hwrite signal value when idle | |||
bit idle_xact_hwrite = 1 | HWRITE?? | rand? |
Constraint: 暂时没加