AHB 协议有哪些版本，区别是什么？

传输模式

INCR

SPLIT

slave memory region
normal mode
split
boot mode

1. AHB2, AHB Lite(AHB3), AHB5 信号列表

1.1 提示

提示：
(AHB original: original black part and red part.)

AHB5 与 AHB Lite 几乎一样。
(AHB-Lite new added:Orange part.)
(AHB4 new added: Blue part)

1.2 信号列表

信号 Name	Source	Destination	方向	位宽	说明
全局信号
HCLK	clock source		时钟 => 总线	1
HRESETn	reset controller		复位 => 总线	1	active LOW to resets the system and bus. This is the only active LOW (AHB-Lite) signal.
来自 master 的信号
HADDR[31:0]	master	slave and decoder	master => bus	max = 64	32-bit system addr bus.
HBURST[2:0]	master	slave	master => bus	max = 3	表明 transfer 是否为 burst 传输的一部分; indicate if the transfer is a singal transfer or forms part of a burst. Fixed lengh bursts of 4, 8 and 16 beats are supported and the burst may be either incrementing or wrapping. (Incrementing bursts of undefined lenght are also supported.) (SINGLE, INCR, WRAP4,INCR4,WRAP8,INCR8,WRAP16,INCR16)
HLOCKx (Locked transfers, AHB2)	master		master => bus		asserted by master to carry out a locked trans. (when HIGH this signal indicates that the master requires locked access to the bus and no other master should be granted the bus until this signal is LOW.)
HMASTERLOCK	master	slave	master => bus		When HIGH, this signal indicates that the current transfer is part of a locked sequence, It has the same timing as the address and control signals.
HBUSREQx (Bus request)	master	master => bus		asserted by master to request access to the bus. (A signal from bus master x to the bus arbiter which indicates that the bus master requires the bus. There is an HBUSREQx signal for each bus master in the system, up to a maximum of 16 bus masters.)
HSIZE2:0]	master	slave	master => bus		indicates size of transfer. （typically size: byte 8-bit, halfword 16-bit or word 32-bit. maximum 1024-bit. ）
HTRANS[1:0]	master	slave	master => bus		indicates the type of transfer beding performed. ( Type: IDLE, BUSY, NONSEQ, SEQ)
HNOOSEC	master	slave and decoder	master =>		Indicates that the current transfer is either a Non-secure transfer or a Secure transfer. This signal is supported if the AHB5 Secure_Transfer property is True.
HEXCL	master	exclusive access monitor	master=>		Exclusive Transfer. Indicates that the transfer is part of an Exclusive access sequence. This signal is supported if the AHB5 Secure_Transfers property is True.
HMASTER[3:0]	master	exclusive access monitor and slave	master =>		Master identifier. Generated by a master if it has multiple Exlusive capable threads. Modified by an interconnect to ensure each master is uniquely identified. This signal is supported if the AHB5 Exclusive_Transfer property is True.
HWDATA[31:0]	master	slave	master => bus		The write data bus transfers data from the master to the slaves during write operations. A minimum data bus width of 32-bit is recommended. This can be extended to enable higher bandwidth operations.
HWRITE	master	slave	master => bus		write signal. 1/0 : write/read. It has the same timing as the address signals, it must remain constant throughout a burst transfer.
HPROT[3:0]	master	slave	master => bus		protection control signals. (保护控制信号提供有关总线访问的附加信息，主要供希望实现某种级别保护的任何模块使用。这些信号表明传输是操作码获取还是数据访问，以及传输是特权模式访问还是用户模式访问。对于带有内存管理单元的总线主机，这些信号还指示当前访问是可缓存的还是可缓冲的。)
HPROT[6:4]	master	slave	master => bus		The 3-bit extentsion of the HPROT signal that adds extended memory types. This signal extension is supported if the AHB5 Extended_Memory_Types property is True.
信号 Name	Source	Destination	方向	位宽	说明
来自 decoder 的信号
HSELx (Slave select)	decoder	slave			Each AHB slave has its own slave select signal HSELx and this signal indicates that the current transfer is intended for the selected slave. This signal is simply a combinatorial decode of the address bus. (When the slave is initially selecetd, it must also monitor the status of HREADY to ensure that the previous bus transfer has completed, before it responds to the current transfer.)
来自 arbiter 的信号
HGRANTx (Bus grant)	arbiter		arbiter => bus
HMASTER[3:0] (master number)	arbiter		arbiter => bus		表明当前哪个master has the owership for addr and control bus (These signals from the arbiter indicate which bus master is currently performing a transfer and is used by the slaves which support SLPIT transfers to determine which master is attempting an access. The timing of HMASTER is aligned with the timing of the address and control signals.)
HMASTERLOCK(Locked sequence)	arbiter(slave)		arbiter => bus		indicates that the current master is performing a locked sequence of transfers. This signal has the same timing as the HMASTER signal.
来自 slave 的信号
HRDATA[31:0] (Read data bus in AHB2)	slave	Multiplexor (AHB Lite)	slave =>		(During read opearations, the read data bus transfers data from the selected slave to the multiplexor. The multiplexor then transfer the data to the transfer. )
HREADY (transfer done) (AHB2)	slave	slave => bus		When HIGH the HREADY signal indicates that a transfer has finished on the bus. This signal may be driven LOW to extend a transfer. Note: Slaves on the bus require HREADY as both an input and an output signal.
HREADYOUT	slave	Multiplexer	slave =>		When HIGH, the HREADYOUT signal indicates that a transfer has finished on the bus. This signal may be driven LOW to extend a transfer. Note: Slaves on the bus require HREADY as both an input and an output signal.
HRESP[1:0] (transfer response, AHB2)	slave		slave => bus		The transfer response provides additional information on the status of a transafer. Four differnent responses: OKAY, ERROR, RETRY and SPLIT.
HRESP (AHB Lite)	slave	Multiplexer	slave => bus		The transfer response, after passing through the multiplexor, provides the master with additional information on the status of a transfer. When LOW, the HRESP signal indicates that the transfer status is OKAY. When HIGH, the HRESP signal indicates that the transfer status is ERROR.
HEXOKAY	slave	Multiplexor	slave =>		Exclusive Okay. Indicated the success or failure of an exclusive transfer. This signal is supported if the AHB5 Exclusive_Transfer property is True.
HSPLITx[15:0] (Split completion request, AHB2)	slave(SPLIT-capable)	slave => bus		This 16-bit split bus is used by a slave to indicate to the arbiter which bus masters should be allowed to re-attempt a split transaction. Each bit of this split bus corresponds to a single bus master.
信号 Name	Source	Destination	方向	位宽	说明
来自 multiplexor 的信号 (AHB Lite, AHB5)
HRDATA[31:0]	multiplexor	master	slave =>		Read data bus, selected by the decoder.
HREADY	multiplexor	master and slave	=>		When HIGH, the HREADY signal indicates to the master and all slaves, that the previous transfer is complete.
HRESP (AHB Lite)	multiplexor	master	=>		The transfer response, selected by the decoder.
HEXOKAY	multiplexor	master	=>		exlusive okay, selected by the decoder.

1.3 block diagram

AHB2

AHB-Lite (AHB3)

AHB 5