【西西学FPGA】Lesson11 VGA

最新推荐文章于 2021-06-08 17:31:36 发布

茶茶酱和FPGA

最新推荐文章于 2021-06-08 17:31:36 发布

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-----------------------------------------------作业二代码-----------------------------------------------
module white_blank(
        input wire sclk,
        input wire s_rst_n,

        output reg h_sync,
        output reg v_sync,
        output reg [2:0] vga_red,
        output reg [2:0] vga_green,
        output reg [1:0] vga_blue
        );
        reg [9:0] h_sync_cnt;
        reg [9:0] v_sync_cnt;
        reg clk_25mhz;
        reg [25:0] clk_cnt;

        reg [9:0] x;
        reg [9:0] y;
        reg [10:0] x_tmp;
        reg [9:0] y_tmp;
// reg [9:0] x_spot;
// reg [9:0] y_spot;
        reg x_flag;
        reg y_flag;

parameter
        CLK_CNT = 26'd80_0000,
        X_SPOT = 10'd400,
        Y_SPOT = 10'd280,
        H_SYNC = 10'd799,
        V_SYNC = 10'd524;

//x;
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                x <= 10'd0;
        else if ((x_flag == 1'b0)&&(clk_cnt == CLK_CNT))
                x <= x + 1'b1;
        else if ((x_flag == 1'b1)&&(clk_cnt == CLK_CNT))
                x <= x - 1'b1;
//x_tmp;
always@(posedge sclk or negedge s_rst_n )
        if(!s_rst_n)
             x_tmp <= 10'd0;
        else if ((x_tmp == 10'd881)&&(clk_cnt == CLK_CNT))
                x_tmp <= 10'd0;
        else if (clk_cnt == CLK_CNT)
                x_tmp <= x_tmp + 1'b1;

//x_flag;
always@(posedge sclk or negedge s_rst_n )
        if(!s_rst_n)
                x_flag <= 1'b0;
        else if((x_tmp <= 10'd440)&&(clk_cnt == CLK_CNT))
                x_flag <= 1'b0;
        else if ((x_tmp > 10'd440)&&(clk_cnt == CLK_CNT))
                x_flag <= 1'b1;

//y
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                y <= 10'd0;
        else if ((y_flag == 1'b0)&&(clk_cnt == CLK_CNT))
                y <= y + 1'b1;
        else if ((y_flag == 1'b1)&&(clk_cnt == CLK_CNT))
                y <= y - 1'b1;
//y_tmp;
always@(posedge sclk or negedge s_rst_n )
        if(!s_rst_n)
             y_tmp <= 10'd0;
        else if ((y_tmp == 10'd559)&&(clk_cnt == CLK_CNT))
                y_tmp <= 10'd0;
        else if (clk_cnt == CLK_CNT)
                y_tmp <= y_tmp + 1'b1;

//y_flag;
always@(posedge sclk or negedge s_rst_n )
        if(!s_rst_n)
                y_flag <= 1'b0;
        else if((y_tmp <= 10'd279)&&(clk_cnt == CLK_CNT))
                y_flag <= 1'b0;
        else if ((y_tmp > 10'd279)&&(clk_cnt == CLK_CNT))
                y_flag <= 1'b1;

//clk_cnt //1s信号
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                clk_cnt <= 26'd0;
        else if (clk_cnt == CLK_CNT)
                clk_cnt <= 26'd0;
        else
                clk_cnt <= clk_cnt + 1'b1;

//clk_25mhz;
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                clk_25mhz <= 1'b1;
        else
                clk_25mhz <= ~clk_25mhz;

//h_sync_cnt;
always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                h_sync_cnt <= 10'd0;
        else if (h_sync_cnt == H_SYNC)
                h_sync_cnt <= 10'd0;
        else
                h_sync_cnt <= h_sync_cnt + 1'b1;

//v_sync_cnt;
always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                v_sync_cnt <= 10'd0;
        else if ((v_sync_cnt == V_SYNC)&&(h_sync_cnt == H_SYNC))
                v_sync_cnt <= 10'd0;
        else if (h_sync_cnt == H_SYNC)
                v_sync_cnt <= v_sync_cnt + 1'b1;

//h_sync,
always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                h_sync <= 1'b1;
        else if (h_sync_cnt <= 10'd95)
                h_sync <= 1'b0;
        else
                h_sync <= 1'b1;

//v_sync,
always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                v_sync <= 1'b1;
        else if (v_sync_cnt <= 10'd1)
                v_sync <= 1'b0;
        else
                v_sync <= 1'b1;

//vga_red,
//vga_green,
//vga_blue
always@(posedge clk_25mhz or negedge s_rst_n)
        if(!s_rst_n)
                {vga_red,vga_green,vga_blue} <= 8'b0;
        else if ((h_sync_cnt <= (10'd343 + x))&&(h_sync_cnt >= (10'd143+ x))&&(v_sync_cnt <= (10'd234 + y))&&(v_sync_cnt > (10'd34 + y)))
                                                 {vga_red,vga_green,vga_blue}<= 8'b11111111;
        else if((v_sync_cnt <= 10'd514)&&(v_sync_cnt > 10'd 354)&&(h_sync_cnt <= 10'd783)&&(h_sync_cnt >= 10'd143))
                                                {vga_red,vga_green,vga_blue}<= 8'b00000011;
        else if((v_sync_cnt <= 10'd354)&&(v_sync_cnt > 10'd 194)&&(h_sync_cnt <= 10'd783)&&(h_sync_cnt >= 10'd143))
                                                      {vga_red,vga_green,vga_blue}<= 8'b00011100;
        else if((v_sync_cnt <= 10'd194)&&(v_sync_cnt > 10'd 34)&&(h_sync_cnt <= 10'd783)&&(h_sync_cnt >= 10'd143))
                                                      {vga_red,vga_green,vga_blue}<= 8'b11100000;
        else
                                                {vga_red,vga_green,vga_blue} <= 8'b00000000;

endmodule
-------------------------------------2016.4.5------------------------------------------
VGA 笔记
1 图片切换速度大于24HZ，遮掩效应。
2 带宽红8bit 256 绿8bit 256 蓝 8bit 256
        分辨率 640（pixel）*480 （row） 1 pixel= 一个RGB
        带宽（bps）=60（HZ）*H*V* 24 = 421.875 Mbps
        所需要的时钟：（数据需要存储到sram中，考虑读写效率问题）
        HSYNC：水平同步信号，行同步
        VSYNC：

        写完一行，行计数器加1；525，有效480；

--------------------------------2016.4.3------------------------------------
1uart + fpga+ram
2 vga
行同步，场同步
屏幕显示的原理

作业：
1屏幕显示三原色，
2有一个200*200在屏幕范围内弹跳
3 在2的基础上做出透明的效果。