brief note on Makefile

usage scene:

compile source code on Unix

auto compilation of the whole project

content:

instructions (like shell)

command “make”:

compile (+pack) + link

file "makefile":

tell command "make" how to compile & link 

brief flow:

1) if the project has not been compiled before, compile all of the source files and link the target program

2) if it is compiled before and there's some files modified, compile the modified ones and link the target program

3) if the head file is modified, recompile the files that refer to it and relink the target program

A Sample(from wiki.ubuntu):

edit : main.o kbd.o command.o display.o \
		insert.o search.o files.o utils.o       /*comments:if the .o files are modified then the following command will launch*/
	cc -o edit main.o kbd.o command.o display.o \
		insert.o search.o files.o utils.o

main.o : main.c defs.h
	cc -c main.c
kbd.o : kbd.c defs.h command.h
	cc -c kbd.c
command.o : command.c defs.h command.h
	cc -c command.c
display.o : display.c defs.h buffer.h
	cc -c display.c
insert.o : insert.c defs.h buffer.h
	cc -c insert.c
search.o : search.c defs.h buffer.h
	cc -c search.c
files.o : files.c defs.h buffer.h command.h
	cc -c files.c
utils.o : utils.c defs.h
	cc -c utils.c
clean :
	rm edit main.o kbd.o command.o display.o \
		insert.o search.o files.o utils.o

how dose make work:

1. find the file with the name "Makefile" or "makefile" in current folder

2. if found, make process will find the first target as the final target (in the sample code above, the target is file "edit")

3. if the file edit dose not exit, or the .o files are modified after they were linked, then make will execute the following shell code to emerge the file edit

4. if the .o files that file edit depends on dose not exit too, find the lines that describe it and run the command

5.  so, at the beginning, make will create the .o files and then links them to be the final target 

6. ADDITION: if the file, like file clean, does not have connections with other files, we can put it in an explicit command like "make clean" to do some special functions

parameter in makefile(sample comes from wiki.ubuntu):

objects = main.o kbd.o command.o display.o \
		insert.o search.o files.o utils.o

edit : $(objects)
	cc -o edit $(objects)

let make auto emerge(default feature):

objects = main.o kbd.o command.o display.o \
		insert.o search.o files.o utils.o
 cc = gcc

edit : $(objects)
	cc -o edit $(objects)

main.o : defs.h
kbd.o : defs.h command.h
command.o : defs.h command.h
display.o : defs.h buffer.h
insert.o : defs.h buffer.h
search.o : defs.h buffer.h
files.o : defs.h buffer.h command.h
utils.o : defs.h

.PHONY : clean  /*to show that the clean is a fake target*/
clean :
	rm edit $(objects)

make can let you collect the .h and .c files together, however, i don't like it, so let it go~O(∩_∩)O~

everthing above comes from wiki.ubuntu