PCIe学习笔记（31）--- PL-Logical (Gen 1 and Gen 2) --- (3)

Rx clock: data bit transitions

Local clock

different between, compensation needed

Link training: TS1/2, bit lock

low power state, such as L0s, or L1, lose synchronization.

transmitter sends an electrical idle ordered set EIOS before going to lower power state (发EIOS的原因)

wake from L0s, sends FTS ordered set

from L1, sends TS1 order set

因为L0s呆的时间比较短，receiver PLL没有偏离Tx clock太大

Comma (COM) 是起SYMBOL LOCK的作用， 前提是已经BIT LOCK

COM的组成： 0011-1110-10 OR 1100-0001-01， 因为包含五个连续的BIT，所以，非常容易detectable

TS1/TS2, FTS均包含了COM

之前，说过TX,RX的CLOCK +/-300 ppm (parts per million) of center frequency

worst between them could be 600 ppm, 

elastic buffer

进入的时候，使用的是recovered clock

出去的时候，使用的是local clock

假如recovered clock慢于local clock, buffer 趋于underflow, 则加入SKP OS

假如recovered clock快于local clock, buffer趋于overflow, 则删除SKP OS

lane-to-lane skew

source:

difference between electrical drivers and receivers

printed wiring board impedance variations

trance length mismatches

通过OS来做DE-SKEWING

多条LANE中，COM先到的，则被安排DELAY，直到所有LANE都同步了

8b/10b decoder

要做disparity error check (Code violation and Disparity error Detection)

CRD: Current Running Disparity

书中举了个栗子，Disparity error可能被检测到的时候，会延时

descrambler:

k character or os not scrambled at the transmitter

有更多的关于scrambler的规则

byte un-striping (striping的反向)

RX BUFFER：

只有TLPs与DLLPs

Extended Advanced Error Capabilities register set

receiver error status bit in the correctable error status register

device send an err_cor message to the RC