module even_div
(
clk,
rst_n,
clkout
);
input wire clk;
input wire rst_n;
output reg clkout;
parameter N=4;
parameter WIDITH=3;
reg [WIDITH-1:0]cnt;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cnt<=0;
clkout<=0;
end
else
begin
if(cnt==N/2-1)
begin
clkout<=~clkout;
cnt<=0;
end
else
begin
cnt<=cnt+1'b1;
end
end
end
endmodule
testbench:
`timescale 1ns/1ns
module even_div_tb;
reg clk;
reg rst_n;
wire clkout;
initial
begin
clk=0;
rst_n=0;
#1000 rst_n=1;
end
always #10 clk=~clk;
even_div even_div
(
.rst_n(rst_n),
.clk(clk),
.clkout(clkout)
);
endmodule