FPGA实现任意分频

module odd_div
(
	clk,
	rst_n,
	clkout
);

input  wire clk;
input  wire rst_n;
output reg clkout;


parameter HIGH_WIDITH=3;
parameter LOW_WIDITH=2;
parameter N=3;

reg [N-1:0]cnt;
reg state;

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		begin
			cnt<=0;
			clkout<=0;
			state<=0;
		end
	else
		case(state)
		0:if(cnt<LOW_WIDITH-1)
			begin
				cnt<=cnt+1'b1;
				state<=0;
			end
		  else
		    begin
			    cnt<=0;
				clkout<=1;
				state<=1;
			end
		1:if(cnt<HIGH_WIDITH-1)
			begin
				cnt<=cnt+1'b1;
				state<=1;
			end
		  else
		    begin
				cnt<=0;
				clkout<=0;
				state<=0;
			end
		default :state<=0;
		endcase
end

endmodule;

testbench：

`timescale 1ns/1ns
module odd_div_tb;

reg clk;
reg rst_n;

wire clkout;

initial 
	begin
		clk=0;
		rst_n=0;
		#1000 rst_n=1;
	end

always #10 clk=~clk;




odd_div odd_div
(
	.rst_n(rst_n),
	.clk(clk),
	.clkout(clkout)
);
endmodule