一、特点:
同步复位:用Verilog描述如下:
always @ (posedge clk) begin
if (!Rst_n)
...
end
异步复位:用Verilog描述如下:
always @ (posedge clk,negedge Rst_n) begin
if (!Rst_n)
...
end
异步复位同步释放(将异步信号同步化):用Verilog描述如下:
always @ (posedge clk)
rst_nr <= rst_n; //现将异步复位信号用同步时钟打一拍
always @ (posedge clk or negedge rst_nr)
if(!rst_nr) b <= 1'b0;
else b <= a;
always @ (posedge clk or negedge rst_nr)
if(!rst_nr) c <= 1'b0;
else c <= b;
二、总结:
同步复位消耗资源较多,异步复位容易出现亚稳态,一般推荐异步复位,同步释放。