好的，以下是Verilog语言写的1位和8位加法器主文件和tb测试文件：
1位加法器主文件：
```verilog
module half_adder(
input a,
input b,
output sum,
output carry
);
assign sum = a ^ b;
assign carry = a & b;
endmodule
module full_adder(
input a,
input b,
input cin,
output sum,
output cout
);
wire h1, h2, h3;
half_adder ha1(.a(a), .b(b), .sum(h1), .carry(h2));
half_adder ha2(.a(h1), .b(cin), .sum(sum), .carry(h3));
assign cout = h2 | h3;
endmodule
module one_bit_adder(
input a,
input b,
input cin,
output sum,
output cout
);
full_adder fa(.a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));
endmodule
```
8位加法器主文件：
```verilog
module eight_bit_adder(
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] sum,
output cout
);
wire c[8];
one_bit_adder oba0(.a(a[0]), .b(b[0]), .cin(cin), .sum(sum[0]), .cout(c[0]));
one_bit_adder oba1(.a(a[1]), .b(b[1]), .cin(c[0]), .sum(sum[1]), .cout(c[1]));
one_bit_adder oba2(.a(a[2]), .b(b[2]), .cin(c[1]), .sum(sum[2]), .cout(c[2]));
one_bit_adder oba3(.a(a[3]), .b(b[3]), .cin(c[2]), .sum(sum[3]), .cout(c[3]));
one_bit_adder oba4(.a(a[4]), .b(b[4]), .cin(c[3]), .sum(sum[4]), .cout(c[4]));
one_bit_adder oba5(.a(a[5]), .b(b[5]), .cin(c[4]), .sum(sum[5]), .cout(c[5]));
one_bit_adder oba6(.a(a[6]), .b(b[6]), .cin(c[5]), .sum(sum[6]), .cout(c[6]));
one_bit_adder oba7(.a(a[7]), .b(b[7]), .cin(c[6]), .sum(sum[7]), .cout(cout));
endmodule
```
测试文件：
```verilog
module tb_eight_bit_adder;
reg [7:0] a, b;
reg cin;
wire [7:0] sum;
wire cout;
eight_bit_adder eba(.a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));
initial begin
a = 8'b00000000;
b = 8'b00000000;
cin = 0;
#10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);
a = 8'b00000000;
b = 8'b00000001;
cin = 0;
#10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);
a = 8'b00000001;
b = 8'b00000001;
cin = 0;
#10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);
a = 8'b11111111;
b = 8'b11111111;
cin = 0;
#10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);
a = 8'b00000001;
b = 8'b00000001;
cin = 1;
#10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);
a = 8'b11111111;
b = 8'b11111111;
cin = 1;
#10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);
$finish;
end
endmodule
```
以上是1位和8位加法器的Verilog代码和测试文件的示例。请注意，这只是一个简单的示例，实际的电路可能需要更多的测试和调试。
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